SpaceCube IRAD

LOGO.
049
The Shape of Things to Come
Goddard Space Flight Center
SpaceCube IRAD Development Effort

John Godfrey Code 561
SpaceCube Development Team 26 June 2006
SpaceCube Architecture
SpaceCube IRAD Overview
What is SpaceCube?
SpaceCube is a Goddard IRAD effort to produce a generic, high density user-configurable subsystem. It is intended for applications which require a large amount of processing power and flexible interfaces with minimal mass, power, and cost. SpaceCube utilizes cutting edge reconfigurable FPGA technology, combined with a Rad-Hard by Architecture approach to allow for a large amount of logic in a small package. SpaceCube is capable of performing as a high speed network router, instrument C&DH or communications adaptor.
WARNING: INFORMATION SUBJECT TO U.S. EXPORT CONTROL LAWS. This document contains technical data within the definition of the International Traffic in Arms Regulations (ITAR) and is subject to the export control laws of the U.S. Government.
26 June 2006
SpaceCube Development Team
SpaceCube IRAD History
The SpaceCube concept was originally developed for the Hubble Robotic Servicing and De-orbit Mission (HRSDM) to handle the need for high speed video processing, Pose estimation and routing to the space network. After HRSDMs cancellation, SpaceCube became an independent IRAD effort for approximately 8 months before becoming a center-funded IRAD effort in Jan 2006. Currently, SpaceCube is baselined to perform a verification flight on HST SM 4 as the Relative Navigation System (RNS) C&DH, Pose Processing unit and Bi-Static GPS Processor. Currently, RNS is scheduled for flight readiness in December, 2007.
26 June 2006
SpaceCube IRAD Architecture
SpaceCube uses a stacked architecture composed of cards or slices connected via a connector running the length of the stack Slices can be made redundant and the stacking architecture allows any slice to communicate with any other slice thus allowing card level redundancy. Each slice has an individual enclosure which encloses it on 5 sides. Slices are stacked in whatever order desired and covered by a top plate. Up to two Power slices can be combined in a stack (one on the top, one on the bottom) to allow for a complete warm back-up system.
26 June 2006
SpaceCube IRAD Interfaces
Slice to Slice communications are handled via a combination of configurable high and low speed serial links.
High Speed Bus
Virtex IV
SpaceRISC Microcontroller
Voter
Virtex IV
Redundant I2C Busses (100/400 Kb/S) provide for low speed command and telemetry functions High Speed busses such as Ethernet or SpaceWire provide for high speed communications (125Mb/s 250 Mb/s per bus)
I2C
Processor Slice
SpaceRISC Microcontroller
Current implementation can handle up to 6 high speed busses and two low speed busses on the stack. I2C Communication is from hard microcontroller to hard microcontroller for critical functions.
Power Slice
q
Slices can be configured with a variety of front panel options using either RS-422 or LVDS.
SpaceCube can handle 8 full duplex Ethernet or SpaceWire links per processor slice.
Removable front panels allow for differing connector configurations

Default for Processor Slice is 2 51 pin MDM connectors.
26 June 2006
SpaceCube Architecture Space Cube IRAD Baseline Capabilities

ETHERNET CAPACITY
8 x Ethernet Media Access Controllers
IEEE 802.3 compliant 10, 100, 1000 Mb/s Supports MII, GMII Does not use any system gates.
SPECIFICATIONS
CENTRAL PROCESSORS
4 x 450 MHz PowerPC 405, 32-bit RISC processors:
2 x Xilinx XC4VFX60 Redundant to handle SEFI 32K bytes of secondary (L2) on-die cache
DIGITAL SIGNAL PROCESSING 128 XtremeDSP Slices 18-bit by 18-bit, two's complement multiplier with full precision 36-bit result, sign extended to 48 bits.
Common Processor Features are:700+ DMIPS RISC core 32-bit Harvard architecture 16 KB 2-way set-associative instruction and data caches
Auxiliary Processor Unit (APU) controller 1.2V core voltage
FLASH EPROM
256 Mbyte of Flash EPROM application storage Flash has separate power switching.
Allows Flash to be powered off when not in use.
RECONFIGURABLE RESOURCES
2 x 56,880 logic cells 2 x 25,280 slices 2 x 4,176 Kb block RAM 232 18K block RAMs Example: Helion AES core
447 slices, 10 block RAM, 2548Mbps performance
ROM
256 Mbyte of ROM application storage backup for Flash SOFTWARE SUPPORT Support for Linux, VxWorks
WindRiver MontaVista, BlueCat
DRAM 3Dplus stacked SDRAM 4 Gbit 75 MHz Each processor has 1 Gbit dedicated.
GNU GCC Compiler
26 June 2006
SpaceCube Architecture Space Cube IRAD Baseline Capabilities
SERIAL INTERFACES
32 x LVDS serial pairs:
Support Ethernet, SpaceWire, or custom interface. 16550 compatible UARTs Aeroflex LVDS drivers and Receivers RS422 can be substituted for LVDS if desired
ELECTRICAL SPECIFICATION
21V to 35V voltage input through optional low voltage power converter card slice Power Slice can provide: +5V@ 2 Amps +3.3V@ 6 Amps +2.5V@ 4 Amps all voltages are tolerant to +10% / -10%
STACKING CONNECTOR INTERFACE

Airborne Connector: 72 pins Design uses no backplane or motherboard. Low speed internal bus 400Kbps Redundant I2C High speed bus TBD Redundant Power Pins 3.3V, 5V
SAFETY
SDRAM power is switched separately to handle any potential latchup conditions.
ENVIRONMENTAL SPECIFICATION
-20 C to +55 C (operating Baseplate temperature) -40 C to +85 C (storage baseplate temperature) 10% to 90% Relative Humidity, non-condensing (storage)
RAD-HARD SCRUBBER
UT6325 RadHard Eclipse FPGA 320,000 usable system gates 24 dual-port RadHard SRAM modules RadHard to 300K rad(Si)/sec
MECHANICAL SPECIFICATION
4 inches x 4 inches (PCB) Box slice 4.25 inches x 4.25 inches x .75 inches/slice single board, double sided I/O connectors:
72 pin, Airborne Stacking 2 x 37 pin LVDS
OTHER PERIPHERAL INTERFACES

Available through stacking connector by additional card slices Low Voltage Power Converter card slice
Same board size as processor Provides low voltages from spacecraft bus voltage Has 1553 interface, transformers and signal drivers
26 June 2006
SpaceCube Architecture SpaceCube IRAD Components

Switched Fabric Backplane
SpaceCube Processor Slice
LVDS
1.5 in.
Power Slice
Power In
The Processor Slice is the brains of the stack and contains the four central processors (PowerPC 405s) as well as a small RISC microcontroller to provide support and to mitigate single event effects in the PowerPCs.
Processor slice contains the Cubes high speed external interfaces Upto 8 SpaceWire or Ethernet ports per slice. Each PowerPC is capable of providing up to 712 Dhrystone MIPS and has access to approximately 3 million reconfigurable gates. The Processor Slice can be combined with additional processor slices to provide additional computing power or for redundancy.
4 in.
The basic SpaceCube consists of a single SpaceCube Processor Slice (SCuP) and its Power converter (LVPC) Slice Power Slice forms the Base of the SpaceCube.
Power Slice provides regulated low voltages from an unregulated 28V supply. Power Slice also provides support functions such as A/D Conversion for housekeeping, POR circuitry, and MILSTD-1553B Communication.
26 June 2006
SpaceCube IRAD Processor Slice
SpaceCube processor slice is a miniaturized C&DH system on a single 4 x 4 inch board Processing power is provided by 4 PowerPC 405 processors which can be run either in parallel for speed or in a quad redundant voting scheme for SEU immunity
Each PowerPC has its own independent SDRAM for program code/OS use.
Xilinx
4 Dplus 44 x 4 4M 4 SDRAM 44 4 MB
Floating Point 4 4KB 4 Cash
SDRAD Controler
4in x 4in
SDRAD Controler
XC4 44 VFX
IBM Power PC 44 4 44 4 MHz
44 44 SoftCore

4 X Ethernet MAC(HC)
LVDS/444 4X Transmit 4X Receive
4 x
SpaceWire/ Ethernet
3 Pin 3 MDM
LVDS/444 4X Transmit 4X Receive
Xilinx
SDRAM Controller
XC4 44 VFX
IBM Power PC 44 4 44 4MHz
44 44 SoftCore
4 Dplus
SDRAM Controller
4 x
SpaceWire/ Ethernet

4 X Ethernet MAC(HC)
44 x 4 4M 4 SDRAM 44 4 MB
4 Pin 4 MDM
A soft-core SpaceRISC microcontroller is instantiated in the radiation hardened Aeroflex FPGA and acts as the monitor and controller for the PowerPCs and the Virtex logic.
SpaceRISC is instruction set compatible with the PIC16F86 Microcontroller SpaceRISC is responsible for loading/reloading the PowerPC code and scrubbing the Virtex configuration memory. SpaceRISC is also the I2C controller
44Volt . 44Volt . 33Volt .
33 33
Xilinx Bus I/O

I4 Serial Port #4 C I4 Serial Port #4 C
AEROFLEX UT4444 44 RAM Kb

RAD-HARD
44 4 MB Flash 4 DPlus
Serial ROM 4 Mb 4
AeroFlex IO
4 Pin Stack Connector 4
Micro Controller
44 4 MB Flash 4 DPlus
26 June 2006
LVDS/ 4 4 4 R /T ) 4( 4
4 MDM 4
LVDS/ 4 4 4 R /T ) 4( 4
4 M DM 4
RAM RAM
RAM RAM
Power PC
X ilin x 3 P3 V 3 X ilin x 4 P4 V 4
Power PC
Ind e pe n d e n t L a tc h u p S u pp l y In d ep e nd e n t L a tc hu p S u p pl y
In d ep e nd e n t L atc hu p S u p pl y
RA M uP C on fig u r ati o n I/O B uffe ri n g V e ri fi c a ti on R e fr e s h V a l i d ati o n
In de p en de n t L atc h u p S u p pl y
SpaceCube Processor Slice provides configurable LVDS (or RS-422) I/O which can be used with IP Cores to implement a variety of interfaces such as SpaceWire, Ethernet, USB and CameraLink. Cores are available to perform most encoding functions: Reed-Solomon, Convolutional, AES Decryption.
A E RO F LE X
FLAS H FLASH
In de p e n d en t La tc hu p S u p pl y
T e m p er a tu r e
I4 (4 I4 (4 C ) C )
In d e p en d en t L a tc h u p S u pp l y
RO M
3 P i n S ta c k i ng C o nn e c to r 3
Top B o tto m
26 June 2006
Processor Performance
44 44 44 44 Flight Processors Com m ercial Processors
Drhystone MIPS (Integer) Whetstone MIPS (Floating Point)
44 44
MIPS / MFLOPS
44 44
44 4
44 4
44 4
44 4
4 Mongoose 4 (44 Mhz)
Rad 4444 GD Coldfire (44 (44 Pow erPC 333 Rad 444 e ( 444SpaceCube Pentium III (444 SpaceCube Blue Gene PPC PPC 444 Mhz) Mhz) Mhz) (444 Mhz) Mhz) PPC 444 ( 444 4 4(.4Ghz) 4 Mhz) (444 Mhz)
Processor
26 June 2006
26 June 2006
Radiation Mitigation & Redundancy
SpaceCube Processor Slice utilizes Xilinx Virtex devices to perform many of its core functions.
These devices have a very high total dose tolerance, but are susceptible to SEUs. To eliminate the SEU effects, QMR (Quad Module Redundancy) is used. In a QMR scheme, the design is instantiated four times, twice in each Xilinx. These are voted together and if one output is different, it is discarded. User logic is scrubbed to prevent SEUs from corrupting instantiated designs. Processors are hard cores within the devices. SEU performance of processor cores Tested by GSFC in September 05.
PowerPC
PowerPC
PowerPC
PowerPC
Logic
Logic
Logic
Logic
Voter
SpaceRISC
Each Virtex device is split into two functional units consisting of a processor and its peripherals
Device level floor planning is used to ensure that two instantiations are physically separate to reduce the effects of multi-bit SEUs.
26 June 2006
Radiation Mitigation (Voting)
Two types of voting are implemented in SpaceCube

Packet Based Voting is used for low volume, high reliability data generated by the PowerPCs. This data is sent to the SpaceRISC via serial port and voted on byte by byte by the SpaceRISC. Stream Based Voting is used for high volume data such as Ethernet or SpaceWire. Stream data is buffered using FIFOs within the Virtex, then sent to hard voters in the Aeroflex and voted bit by bit. Synchronization is handled by the Aeroflex.
N
M
o 4d
u
e
I4 C M
o 4d
u
e
I4 C M
o 4d
u
e
I4 C M
o 4d
u
e
I4 C
S4 M M S4 M K T M
S4 M M S4 M K T M
S4 M M S4 M K T M
S4 M M S4 M K T M
X A
N 4 N 4 M V N4 N 4 s 4e ( ) N 4 N4 M V N 4 S4 M o t e N 4 u s 4e ( ) N 4 ) T V M o t e r u ) s 4e ( ) K V u - B a n d u s 4e ( o t e r ) ) I4 V C N4 N 4 N4 N 4 N4 N 4 N4 N 4 N4 N 4
i l in x r o f l e
S4 M u o t e r )
o u e t r 4r (
o u e t r 4r (
N4 u s 4e ( ) )
o u e t r 4r (
o u e t r 4r (
o t e r
o u e t r 4r (
For each output channel (e.g. MSM1, MSM2, Ku-band downlink, etc.) there are: Four Parallel-Input-Serial-Output FIFOs (one per Xilinx PowerPC, located in Xilinx) One Control Line from Aeroflex to Xilinx(s) to initiate FIFO serial output One 4-input voter in Aeroflex SCuP board has four synchronous serial lines from Xilinx to Aeroflex (one per PowerPC) SCuP board has one synchronous serial line from Aeroflex to all four Xilinx PowerPCs.
Errors detected and corrected by either voting scheme are reported to the SpaceRISC for inclusion in telemetry.
26 June 2006
SpaceCube IRAD Power Slice
q
I/O Connector RS-444 Driver
Stacking Connector
Buffer
SpaceCube Power Slice provides regulated DC power to the assembled stack.

Provides 5.0 V, 3.3 V, 2.5V, 1.8V 1.2V is locally regulated on Processor slice from the 1.8V supply
V/F Converter
Power Connector
MIL-STD44 44 Driver/ Reciever
MSK 3.3 4V .4 Switching Regulator
MSK 4V .4 Switching Regulator
MSK 4V .4 Switching Regulator VPT 44 4 V to V DC-DC Converter
Power Slice also provides MILSTD-1553B transceivers and transformer.

1553 is controlled remotely from the Processor Slice.
Power Slice provides A/D conversion capability to the stack for housekeeping using a 16 channel Trios ASIC.
Provides voltage monitoring for all Power Slice generated voltages Provides internal temperature monitoring
26 June 2006
SpaceCube IRAD Power Slice
1553 Transformer
5V DC-DC Converter
2.5V DC-DC Converter 3.3V DC-DC Converter
RS-422 Drivers
1.8V DC-DC Converter

26 June 2006
SpaceCube IRAD Current Status
SpaceCube Hardware tested and work has begun on SpaceCube software. 4 EDU PCBs were delivered to the SpaceCube team in Nov 05 All have been tested and are serving as platforms for software/VHDL development
1 Processor Slice delivered to ELC software team in early May 06. 1 Processor Slice / Power Slice delivered June 22, 2006 to CCA Team.
Voting Scheme Development is continuing, initial version is currently in testing. Flight Ethernet (D/S) port is currently in progress. RNS on SM 4 will be using SpaceCube and is currently scheduled for flight readiness in Dec 2007.
q
Processor Slice Stacked on Power Slice
Porting of Linux OS is currently in process

Linux OS Training was held in June. cFE is being ported to Linux and will be ported to SpaceCube.
26 June 2006

SpaceCube IRAD

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LOGO.

The Shape of Things to Come

Goddard Space Flight Center

SpaceCube IRAD Development Effort

SpaceCube Development Team 26 June 2006

The Shape of Things to Come

Goddard Space Flight Center

SpaceCube Development Team

The Shape of Things to Come

Goddard Space Flight Center

SpaceCube Development Team

The Shape of Things to Come

Goddard Space Flight Center

SpaceCube Development Team

The Shape of Things to Come

Goddard Space Flight Center

Removable front panels allow for differing connector configurations

SpaceCube Development Team

The Shape of Things to Come

SpaceCube Architecture Space Cube IRAD Baseline Capabilities

Goddard Space Flight Center

Auxiliary Processor Unit (APU) controller 1.2V core voltage

GNU GCC Compiler

SpaceCube Development Team

The Shape of Things to Come

SpaceCube Architecture Space Cube IRAD Baseline Capabilities

Goddard Space Flight Center

STACKING CONNECTOR INTERFACE

OTHER PERIPHERAL INTERFACES

SpaceCube Development Team

The Shape of Things to Come

SpaceCube Architecture SpaceCube IRAD Components

Goddard Space Flight Center

SpaceCube Processor Slice

SpaceCube Development Team

The Shape of Things to Come

Goddard Space Flight Center

IBM Power PC 33 3 44 4 MHz

IBM Power PC 44 4 44 4 MHz

Xilinx Bus I/O

AEROFLEX UT4444 44 RAM Kb

4 Pin Stack Connector 4

SpaceCube Development Team

The Shape of Things to Come

Goddard Space Flight Center

RA M uP C on fig u r ati o n I/O B uffe ri n g V e ri fi c a ti on R e fr e s h V a l i d ati o n

SpaceCube Development Team

The Shape of Things to Come

Goddard Space Flight Center

Drhystone MIPS (Integer) Whetstone MIPS (Floating Point)

4 Mongoose 4 (44 Mhz)

SpaceCube Development Team

The Shape of Things to Come

Goddard Space Flight Center

SpaceCube Development Team

The Shape of Things to Come

Goddard Space Flight Center

SpaceCube Development Team

The Shape of Things to Come

Goddard Space Flight Center

Two types of voting are implemented in SpaceCube

SpaceCube Development Team

The Shape of Things to Come