Shashank Agarwal Innovation and Incubation labs NEC-HCL

Introduction Routers functionality and generic architecture Abstract Components of a Router

IP Routers Architecture Design Issues on different level of internet Advances and Trends in Router Design Open problems for Routers Design Conclusion

Switch Fabrics Line Cards CPU Host

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Router is layer 3 Packet forwarder

Links global internet Transfer packets from input to output links

Router classification
Backbone Router Enterprise Router Access Router

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Input Port

Output Port

Switching Fabric Input Port Output Port

Routing Processor

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Route processing
path computation routing table maintenance reach ability propagation achieved by control path)

packet forwarding
IP packet validation Destination IP Address Parsing and Table Lookup Packet Lifetime Control Checksum Calculation

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Header Processing
Data Hdr Data Hdr

Lookup Update IP Address Header

IP Address Next Hop

Queue Packet

1M prefixes Off-chip DRAM

Address Table

Buffer Memory

1M packets Off-chip DRAM

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Data

Hdr

Header Processing
Lookup IP Address Update Header

Buffer Manager
Buffer Memory

Data

Hdr

Address Table

Data

Hdr

Header Processing
Lookup IP Address Update Header

Buffer Manager

Data

Hdr

Address Table

Interconnection Fabric

Buffer Memory

Data

Hdr

Header Processing
Lookup IP Address Update Header

Buffer Manager
Buffer Memory

Data

Hdr

Address Table

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Interfaces (Line Cards)

Switching fabric

Input/output of packets Buffering / Queuing QoS Moving packets from input to output
Buses Crossbars Shared memories

Data Plane

CPU Host for running control plane Software(processing module)

Routing Packet processing Scheduling Etc.

Control Plane

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Control Path or Slow Path (consist of the CPU). Data Path or Fast Path (consist of the line card).
Controller card Routing control Topology &Address Exchange

Neighbor nodes

Neighbor nodes

Routing Table
Router Backplane
forwarding

Routing Table

Interface card Packet Forwarding

Incoming data packets

outgoing data packets

a) Basic architecture
b) Routing Components

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Time critical processing tasks forms the critical path. Time critical tasks mainly consist of header checking, forwarding(include segmentation), QoS control. Most high-speed routers implement this fast path in hardware.

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Packets destined to a router, such as maintenance, management or error protocol data are usually not time critical (ICMP,SNMP,TCP,UDP and routing protocol entities RIP, OSPF, BGP etc.)
Packet by Packet Orientation Background Tasks

-Fragmentation and reassembly

-Source routing option -Route recording Option -Timestamp option -ICMP message generation
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-Routing Protocols (RIP, OSPF, BGP, etc)

-Network management(SNMP) -Router configuration(BOOTP, DHCP, etc)

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(1)Shared Medium Switch Fabric: TDM Bus

In this each module is allocated a time slot in continuously repeating transmission. a

limited in capacity and by the arbitration overhead for sharing this critical resource. challenge is that it is almost impossible to build a bus arbitration scheme fast enough to provide nonblocking performance at multigigabit speeds.

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(2)Shared Memory Switch Fabric

Input Port
Packets

Output Port Egress Port

Packets

Ingress Port

Input Port
Packets

Shared Memory

Output Port Egress Port

Packets

Ingress Port

System Controller Bottleneck- speed limited by memory access time and a Egress port Should work at the Total speed of all the ingress ports.
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(3)Distributed Output Buffered Switch Fabric

Independent paths exist between all N2 possible pairs of
inputs and outputs. Unlike the shared medium approach, the address filters and buffers need to operate only at the port speed.
Ingress

1 2 . . N

Buses

AF

AF

AF

AF

AF

AF

Address Filters Buffers

Egress

N
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(4) Space Division Switch Fabric : Crossbar switch

Every input port has a connection to every output port During each timeslot, each input connected to zero or one outputs

Advantage: Exploits parallelism Disadvantage: Need scheduling algorithm

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Problem: The packet at the front of the queue experiences contention for the output queue, blocking all packets behind it.

Input 1 Input 2 Input 3

Output 1 Output 2 Output 3

Maximum throughput in such a switch: 2 sqrt(2)

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Advantages

Easy to build

100% can be achieved with limited speedup

input interfaces

output interfaces
Crossbar

Disadvantages

Harder to design algorithms

Two congestion points Flow control at destination

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Maintain N virtual queues at each input

one per output
Input 1

Output 1 Output 2 Output 3

Input 2

Input 3

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CPU Host for running control plane

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Functions
Computes forwarding table Implement Routing Protocol Run software to configure and manage router Handles packets whose destination address are not in the forwarding table

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GPP tends to be more expensive, but allow extensive port functionality. ASICs are not only cheaper, but can also provide operations that are specific to routing. It is argued that ASIC can reduce the complexity on each system board by combining a number of functions into individual chips that are designed to perform at high speeds.

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Bus-based Router architecture with single Processor

Use general purpose CPU multiple interface cards interconnected through a shared bus.
Processor (CPU

Route

Memory

Bus

DMA

DMA Line Card MAC

DMA

Line Card
MAC

Line Card
MAC

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CPU

Route Table

Buffer Memory

Line Card
Buffer Memory Fwding Cache
MAC

Line Card
Buffer Memory Fwding Cache
MAC

Line Card
Buffer Memory Fwding Cache
MAC

Typically <5Gb/s aggregate capacity

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Architecture with Multiple Parallel Forwarding Engines

Forwarding Engine
Forwarding Engine Forwarding Engine Resource Control

Forwarding Engine Row Bus

Control Bus Forwarding Engine Column Bus Data Bus

Network Interface Network Interface Network Interface

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IP router architectures(4)
Crossbar: Switched Backplane with multiple processors
Route Processor

Line Card Line Card

Forwarding Engine Forwarding Engine

Line Card Switch Fabric

Forwarding Engine

Typically <50Gb/s aggregate capacity

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IP router architectures(5)
Crossbar: Switched Backplane with fully distributed processors
Switch Fabric

Network Interface

Network Interface

Network Interface

Switch Fabric Interface

Inbound Processing

Local Processing Subsystem

Outbound Processing

Media-Specific Interface

Typically >50Gb/s aggregate capacity

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Backbone Router interconnects Enterprise Network

High link cost shared among large customer base.

Main challenge
Maintaining high speed Reliability

Techniques of achieving Reliability

Dual power supplies Hot spares Duplicate data path through routers

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Major performance Bottleneck

Route lookup in Forwarding Table
Routing Table may contain thousand of entries Finding the longest matching prefix Small packet increase cost of lookup Large number of Destination increases cost

Output Qued Routers

Switch Fabric runs faster than sum speed of incoming links Problems:
o Limitation on speed of Router o Rate of accessing output buffers limited by SRAM or DRAM access time.

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Input queued Routers

Problems
Contention for switching fabric and output queue. Difficult to design high speed arbiters that will fairly schedule switch fabric and output lines.

Stability and Reliability of Routing Protocol implementation

Routers running different protocols

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Enterprise/Campus Routers interconnect End system Main Objective

Main challenges

Provide connectivity to large no. of end points as cheaply as possible. Provide different service qualities. Routers have low cost/ports Routers have large no. of ports Easy to configure Support QoS Carry multicast traffic efficiently Support features like traffic filter, firewall and Vlan

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Access Routes link customers at home or in small business with an ISP Main Objective
Support heterogeneous high speed ports Support variety of protocol at each port

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 High speed route lookup

Speed of algorithm determined by
o Number of memory access o Speed of memory

Techniques to improve performance of root lookup algorithm

Hardware oriented techniques
o Based on CAMS and caches

Table compaction techniques

o Build compact data structure for the forwarding table and store in cache Hash based solution o Use markers on the hash tables
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 Advances in switching fabric

ATM switch fabric core
o Allows router to support different QoS stream o Once destination port is determined, IP packet is fragmented into ATM cells and switched o ATM cells are reassembled at output ports before transmission

Enterprise level Mgmt and centralization

Single administrator controlling all routers in the enterprise Centralize some router function
o Central route server computes loop free routes for entire enterprise and loads them on all routers forwarding table.

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 Avoid Route Lookups

Speeding up output queues
o Bottleneck of Output queue is access speed of Buffer o Solutions o Build very wide memories that can load entire cell in a single cycle Input Queued Switches Problems o HOL problem o Arbitrating access to switch fabric at high speed o Difficult to implement scheduling algorithm that simultaneously schedules both fabric and output queues Solutions o VOQ
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 Scheduling
Fair Queuing
o Each packet source sharing a link is allocated a weight at bottleneck link o Protects well-behaved sources from losing packets due to misbehavior of other sources Reducing Port cost Cost depend on o Amount and kind of memory use: SRAMs vs. DRAMs o Processing power: ASIC vs. General purpose processors o Complexity of protocol used for communication between port and routing processor. Soft Router Optics Inside Router

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Flow identification Need efficient and fast flow classifier Ease of Configuration

Software stability of large systems is difficult to achieve

Interaction between bugs from different vendors can lead to persistent network instability

Configuring Router is hard Detecting Mistake in configuration file is difficult Misconfigured routers causes performance problems

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While advances in router design have solved some difficult routing problems, some important issues remain unsolved Trade off between cost , speed, flexibility, and ease of configuration will still be challenge for a router design Routers need enough processing power to forward several million packets per second (Mpps). The major design parameters are
Amount and power of memory Processing Power Complexity of Protocol
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