PRESENTATION ON: VERILOG-2001,SYSTEM VERILOG AND VERILOG-AMS

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PRESENTED BY: TOYA NATH ACHARYA ME in Communication Engineering Kathmandu University

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WHAT IS VERILOG?
Hardware Description Language The Verilog HDL is an IEEE standard - number 1364 Used in the design, verification, and implementation of

digital logic chips at the register transfer level (RTL) level of abstraction Used for verification through simulation, for timing analysis, for test analysis (testability analysis and fault grading) and for logic synthesis.

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HISTORY VERILOG:

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Begining o Invented during

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1983/1984 at

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FEATURE OF VERILOG-2001 : o Comma used in sensitive list always @ (a, b, c, d, e) in verilog-2001 always @ (a or b or c or d or e) in earlier version o Combinational logic sensitive list always @ (*) in verilog-2001 always @ (a or b or c or d or e) in earlier version o In Verilog 1995, default data type is net and its width is 1 bit. In Verilog 2001 the default data type is wire and width is adjusted automatically. o Register data types reg b, c, d = 0; in earlier version reg signed b, c, d = 0; in verilog-2001

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CONTD...... o New operators <<< : Shift left, to be used on signed data type >>> : shift right, to be used on signed data type ** : exponential power operator
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Port Declaration module memory_v95 ( read, write); input read; output write; module memory_v2001 (input read, output write) Multi Dimensions Array reg [7:0] address; in earlier version reg [15:0] array [0:255][0:255]; in verilog-2001
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CONTD...... o A function with added automatic keyword allows the function to be called recursively. o Generate Blocks is possible to use it for loops to produce multiple instants. o File IO In Verilog 1995, file IO was limited to reading hex files into memory array using readmemh and writing file using $display and $monitor. But in Verilog 2001, following operations can performed. C or C++ type file operation (like checking end of file) Reading charaters from file from a fixed location 5/14/12 6 Reading a formated lines in file 6

FEATURE OF SYSTEM-VERILOG : Combines the features of Hardware Description Languages such as Verilog and VHDL with features from specialized Hardware Verification Languages, together with features from C and C++ Improves the productivity,readability,and reusability of verilog based code. SystemVerilog adds important new constructs to Verilog2001, including Supports the C built-in types, with the meaning given by the implementation C compiler SystemVerilog adds string, and class data types SystemVerilog offers several integer data types, representing a hybrid of both Verilog and C data types such as int,longint etc
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CONTD.... Integer types use integer arithmetic and can be signed or unsigned The realdata type is from Verilog-2001, and is the same as a C double. The shortreal data type is a SystemVerilog data type, and is the same as a C float SystemVerilog includes a string data type, which is a variable size, dynamically allocated array of bytes Operator overloading jump statements,returns,break, continue void functions

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CONTD.... default arguments pass by reference Interfaces to encapsulate communication Clocking blocks to support cycle-based methodologies Program blocks for describing tests The procedural assignment operators (<=, =) can now operate directly on arrays. Parameters can be declared any type, including user-defined typedefs

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FEATURE OF VERILOG -AMS: o Derived from IEEE std 1364-2005 Verilog HDL. o Consists of the complete IEEE std 1364-2005 Verilog HDL specification, an analog equivalent for describing analog systems ( Verilog-A ), and extensions to both for specifying the full Verilog-AMS HDL o applicable to both electrical and non-electrical systems description o used to describe discrete (digital) systems and mixed-signal systems o Features: Signals of both analog and digital types can be declared in the same module initial, always, and analog procedural blocks can appear in the same module
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CONTD........ both analog and digital signal values can be accessed from any context (analog or digital) in the same module digital signal values can be set (write ) from any context outside of an analog procedural block analog potentials and flows can only receive contributions (write operations) from inside an analog procedural block when hierarchical connections are of mixed type (i.e., analog signal connected to digital port or digital signal connected to analog port), userdefined connection modules are automatically inserted to perform signal value conversion
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SYSTEM,FLOW AND POTENTIAL: Fig: System

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Fig: Kirchhoffs law

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PROGRAMMING ... o Verilog/AMS is a superset of the Verilog digital HDL so all statements in digital domain work as in Verilog o In analog domain, some new operators are defined, for example the "<+" branch contribution operator applicable to both electrical and non-electrical systems description o module shiftPlus5(in, out); // level shifting voltage follower input in; output out; voltage in, out; //voltage is a signal flow analog begin V(out) <+ 5.0 + V(in); end endmodule
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PROGRAMMING ... o module voltage_amplifier (out, in); input in; output out; voltage out, // Discipline voltage defined elsewhere in; // with access function V() parameter real GAIN_V = 10.0; analog V(out) <+ GAIN_V * V(in); endmodule

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SYNTAX FOR ANALOG PROCEDURAL BLOCK o analog_construct ::= analog analog_statement |analog initial analog_function_statement analog_statement ::= { attribute_instance } analog_loop_generate_statement | { attribute_instance } analog_loop_statement | { attribute_instance } analog_case_statement | { attribute_instance } contribution_statement | { attribute_instance } indirect_contribution_statement | { attribute_instance } analog_event_control_statement analog_statement_or_null ::= analog_statement | { attribute_instance } ;
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CONNECT SPECIFICATION STATEMENTS o specification of which connect module is used, including parameterization, for bridging given discrete and continuous discipline o connectrules_declaration ::= connectrules connectrules_identifier ; { connectrules_item } endconnectrules connectrules_item ::= connect_insertion | connect_resolution

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CONNECT SPECIFICATION EXAMPLE connectmodule elect_to_logic(el,cm); input el; output cm; reg cm; electrical el; ddiscrete cm; endmodule connectmodule logic_to_elect(cm,el); input cm; output el; ddiscrete cm; electrical el; analog V(el) <+ transition((cm == 1) ? 5.0 : 0.0); endmodule connectrules mixedsignal; connect elect_to_logic; 5/14/12 17 connect logic_to_elect; 17

REFERENCES: o Language Reference Manual Analog & Mixed-Signal Extension to Verilog HDL Version 2.3.1 June 1, 2009 Accellera o Language Reference Manual SystemVerilog 3.1a Accelleras Extensions to Verilog o http://www.asic-world.com

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THANK YOU !!!

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