Introduction to VLSI Design

Mosharaf Hossain

March 2012

Course Topics
Introduction to CMOS circuits
MOS transistor theory, processing technology CMOS circuit and logic design

System design methods

CAD algorithms for backend design Case studies, CAD tools, etc.

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CMOS VLSI Design

Bibliography
Textbook Weste and Harris. CMOS VLSI Design (3rd edition) Addison Wesley ISBN: 0-321-14901-7 Available at amazon.com.

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Introduction
Integrated circuits: many transistors on one chip. Very Large Scale Integration (VLSI): very many Complementary Metal Oxide Semiconductor Fast, cheap, low power transistors Introduction: How to build your own simple CMOS chip CMOS transistors Building logic gates from transistors Transistor layout and fabrication Rest of the course: How to build a good CMOS chip
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A Brief History
1958: First integrated circuit Flip-flop using two transistors Built by Jack Kilby at Texas Instruments 2003 Intel Pentium 4 mprocessor (55 million transistors) 512 Mbit DRAM (> 0.5 billion transistors) 53% compound annual growth rate over 45 years No other technology has grown so fast so long Driven by miniaturization of transistors Smaller is cheaper, faster, lower in power! Revolutionary effects on society
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Annual Sales
1018 transistors manufactured in 2003 100 million for every human on the planet
Global Semiconductor Billings (Billions of US$)
200

150

100

50

0 1982

1984

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1996

1998

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Year

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Invention of the Transistor

Vacuum tubes ruled in first half of 20th century Large, expensive, power-hungry, unreliable 1947: first point contact transistor John Bardeen and Walter Brattain at Bell Labs Read Crystal Fire by Riordan, Hoddeson

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Transistor Types
Bipolar transistors npn or pnp silicon structure Small current into very thin base layer controls large currents between emitter and collector Base currents limit integration density Metal Oxide Semiconductor Field Effect Transistors nMOS and pMOS MOSFETS Voltage applied to insulated gate controls current between source and drain Low power allows very high integration
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MOS Integrated Circuits

1970s processes usually had only nMOS transistors Inexpensive, but consume power while idle

Intel 1101 256-bit SRAM Intel 4004 4-bit mProc 1980s-present: CMOS processes for low idle power
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Moores Law
1965: Gordon Moore plotted transistor on each chip Fit straight line on semilog scale Transistor counts have doubled every 26 months
1,000,000,000 100,000,000 Pentium 4 Pentium III Pentium II Pentium Pro Pentium

Integration Levels

10,000,000

SSI:

10 gates

Transistors

1,000,000 Intel386 100,000 8086 10,000 8008 4004 1,000 8080 80286

Intel486

MSI: 1000 gates LSI: 10,000 gates

1970

1975

1980

1985

1990

1995

2000

VLSI: > 10k gates

10

Year

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Corollaries
Many other factors grow exponentially Ex: clock frequency, processor performance
10,000 1,000 4004 8008 8080 100 8086 80286 Intel386 10 Intel486 Pentium Pentium Pro/II/III 1 Pentium 4

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Clock Speed (MHz)

1970

1975

1980

1985

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1995

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Year

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Silicon Lattice
Transistors are built on a silicon substrate Silicon is a Group IV material Forms crystal lattice with bonds to four neighbors
Si Si Si Si Si Si Si Si Si

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Dopants
Silicon is a semiconductor Pure silicon has no free carriers and conducts poorly Adding dopants increases the conductivity Group V: extra electron (n-type) Group III: missing electron, called hole (p-type)
Si Si Si Si Si Si Si Si Si Si Si B Si Si Si

+ -

As Si

Si

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p-n Junctions
A junction between p-type and n-type semiconductor forms a diode. Current flows only in one direction

p-type anode

n-type cathode

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nMOS Transistor
Four terminals: gate, source, drain, body Gate oxide body stack looks like a capacitor Gate and body are conductors SiO2 (oxide) is a very good insulator Called metal oxide semiconductor (MOS) capacitor Source Gate Drain Polysilicon Even though gate is SiO2 no longer made of metal
n+ p n+ bulk Si

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nMOS Operation
Body is commonly tied to ground (0 V) When the gate is at a low voltage: P-type body is at low voltage Source-body and drain-body diodes are OFF No current flows, transistor is OFF
Source Gate Drain Polysilicon SiO2
0

n+ p

n+
S D

bulk Si

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nMOS Operation Cont.

When the gate is at a high voltage: Positive charge on gate of MOS capacitor Negative charge attracted to body Inverts a channel under gate to n-type Now current can flow through n-type silicon from source through channel to drain, transistor is ON
Source Gate Drain Polysilicon SiO2
1

n+ p

n+
S D

bulk Si

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pMOS Transistor
Similar, but doping and voltages reversed Body tied to high voltage (VDD) Gate low: transistor ON Gate high: transistor OFF Bubble indicates inverted behavior
Source Polysilicon SiO2 Gate Drain

p+ n

p+ bulk Si

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Power Supply Voltage

GND = 0 V In 1980s, VDD = 5V VDD has decreased in modern processes High VDD would damage modern tiny transistors Lower VDD saves power VDD = 3.3, 2.5, 1.8, 1.5, 1.2, 1.0,

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Transistors as Switches
We can view MOS transistors as electrically controlled switches Voltage at gate controls path from source to drain
g=0 d nMOS g s s d ON s s s d OFF s d OFF g=1 d ON

d pMOS g

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CMOS Inverter
A
0 1

VDD A Y

GND
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CMOS Inverter
A
0 1 0

VDD OFF
A=1 Y=0

ON
A Y

GND
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CMOS Inverter
A
0 1

Y
1 0

VDD ON
A=0 Y=1

OFF
A Y

GND
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CMOS NAND Gate

A 0 0 B 0 1 Y

Y A B

1
1

0
1

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CMOS NAND Gate

A 0 0 B 0 1 Y 1

ON A=0 B=0

ON Y=1 OFF OFF

1
1

0
1

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CMOS NAND Gate

A 0 0 B 0 1 Y 1 1

OFF A=0 B=1

ON Y=1 OFF ON

1
1

0
1

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CMOS NAND Gate

A 0 0 B 0 1 Y 1 1

ON A=1 B=0

OFF Y=1 ON OFF

1
1

0
1

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CMOS NAND Gate

A 0 0 B 0 1 Y 1 1

OFF A=1 B=1

OFF Y=0 ON ON

1
1

0
1

1
0

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CMOS NOR Gate

A 0 0 B 0 1 Y 1 0

A B Y

1
1

0
1

0
0

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3-input NAND Gate

Y pulls low if ALL inputs are 1 Y pulls high if ANY input is 0

Y A B C
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Compound Gates
Compound gates can do any inverting function Ex: Y A B C D (AND-AND-OR-INVERT, AOI22)
A B (a) C D A B (b) C A (d) D B Y A B (e) C D (f) A B C D Y D B C D

A (c) C A

B C

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Example: O3AI
Y A B C D

A B C D Y D A B C

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CMOS Fabrication
CMOS transistors are fabricated on silicon wafer Lithography process similar to printing press On each step, different materials are deposited or etched Easiest to understand by viewing both top and cross-section of wafer in a simplified manufacturing process

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Inverter Cross-section
Typically use p-type substrate for nMOS transistors Requires n-well for body of pMOS transistors
A GND Y VDD SiO2 n+ diffusion n+ n+ p substrate nMOS transistor pMOS transistor p+ n well p+ p+ diffusion polysilicon metal1

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Well and Substrate Taps

Substrate must be tied to GND and n-well to VDD Metal to lightly-doped semiconductor forms poor connection (used for Schottky Diode) Use heavily doped well and substrate contacts / taps
A GND Y VDD

p+

n+

n+ p substrate

p+ n well

p+

n+

substrate tap

well tap

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Inverter Mask Set

Transistors and wires are defined by masks Cross-section taken along dashed line

GND nMOS transistor substrate tap pMOS transistor well tap

VDD

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Detailed Mask Views

Six masks
n well

n-well
Polysilicon n+ diffusion p+ diffusion Contact Metal
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Metal Polysilicon

n+ Diffusion

p+ Diffusion

Contact

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Fabrication Steps
Start with blank wafer Build inverter from the bottom up First step will be to form the n-well Cover wafer with protective layer of SiO2 (oxide) Remove layer where n-well should be built Implant or diffuse n dopants into exposed wafer Strip off SiO2

p substrate

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Oxidation
Grow SiO2 on top of Si wafer 900 1200 C with H2O or O2 in oxidation furnace

SiO2

p substrate

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Photoresist
Spin on photoresist Photoresist is a light-sensitive organic polymer Softens where exposed to light

Photoresist SiO2

p substrate

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Lithography
Expose photoresist through n-well mask Strip off exposed photoresist

Photoresist SiO2

p substrate

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Etch
Etch oxide with hydrofluoric acid (HF) Seeps through skin and eats bone; nasty stuff!!! Only attacks oxide where resist has been exposed

Photoresist SiO2

p substrate

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Strip Photoresist
Strip off remaining photoresist Use mixture of acids called piranha etch Necessary so resist doesnt melt in next step

SiO2

p substrate

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n-well
n-well is formed with diffusion or ion implantation Diffusion Place wafer in furnace with arsenic gas Heat until As atoms diffuse into exposed Si Ion Implanatation Blast wafer with beam of As ions Ions blocked by SiO2, only enter exposed Si
SiO2 n well

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Strip Oxide
Strip off the remaining oxide using HF Back to bare wafer with n-well Subsequent steps involve similar series of steps

n well p substrate

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Polysilicon
Deposit very thin layer of gate oxide < 20 (6-7 atomic layers) Chemical Vapor Deposition (CVD) of silicon layer Place wafer in furnace with Silane gas (SiH4) Forms many small crystals called polysilicon Heavily doped to be good conductor
Polysilicon Thin gate oxide n well p substrate

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Polysilicon Patterning
Use same lithography process to pattern polysilicon

Polysilicon

Polysilicon Thin gate oxide n well p substrate

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N-diffusion
Use oxide and masking to expose where n+ dopants should be diffused or implanted N-diffusion forms nMOS source, drain, and n-well contact

n well p substrate

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N-diffusion (cont.)
Pattern oxide and form n+ regions

n+ Diffusion

n well p substrate

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N-diffusion (cont.)
Historically dopants were diffused Usually ion implantation today But regions are still called diffusion

n+

n+ n well p substrate

n+

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N-diffusion (cont.)
Strip off oxide to complete patterning step

n+

n+ n well p substrate

n+

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P-Diffusion
Similar set of steps form p+ diffusion regions for pMOS source and drain and substrate contact

p+ Diffusion

p+

n+

n+ p substrate

p+ n well

p+

n+

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Contacts
Now we need to wire together the devices Cover chip with thick field oxide Etch oxide where contact cuts are needed

Contact

Thick field oxide p+ n+ n+ p substrate p+ n well p+ n+

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Metalization
Sputter on copper / aluminum over whole wafer Pattern to remove excess metal, leaving wires

Metal

p+

n+

n+ p substrate

p+ n well

p+

n+

Metal Thick field oxide

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Layout
Chips are specified with set of masks Minimum dimensions of masks determine transistor size (and hence speed, cost, and power) Feature size f = distance between source and drain Set by minimum width of polysilicon Feature size scales ~X0.7 every 2 years both lateral and vertical Moores law Normalize feature size when describing design rules Express rules in terms of l = f/2 E.g. l = 0.3 mm in 0.6 mm process Todays l = 0.01 mm (10 nanometer = 10-8 meter)
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Simplified Design Rules

Conservative rules to get you started

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Inverter Layout
Transistor dimensions specified as Width / Length Minimum size is 4l / 2l, sometimes called 1 unit In f = 0.01 mm process, this is 0.04 mm wide, 0.02 mm long

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Summary
MOS Transistors are stack of gate, oxide, silicon Can be viewed as electrically controlled switches Build logic gates out of switches

Draw masks to specify layout of transistors

Now you know everything necessary to start

designing schematics and layout for a simple circuit!

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