Simple As Possible -1 (SAP-1)

Computer Architecture 2004

SAP-1 Characteristics
Hardwire Architecture 2 8-bit general registers 1 8-bit output registers 4-bit ALU (additional, subtraction) 4-bit instructions and 4-bits operands
(cccc oooo)
cccc = OP CODE oooo = OPERAND

16x8 address ROM for mixed program and data 12 control signals

SAP-1
Architecture

Cp CLK CLR Ep
Program Counter (PC) 4

8 A register 8

La CLK Ea
8

Lm CLK
(Memory Address Register) MAR 4 8 Arithmetic Logic Unit ALU

Su

Eu
4 8 8

Lb
16x8 PROM 8 8 B register

CLK

Er

Li CLK CLR Ei
Instruction Register (IR)

8 8 4

Lo
Output register

CLK

Control Unit CON

CLK CLR

Binary Display D

CpEpLmEr LiEiLaEa SuEuLbLo

12

Program Counter
OUTPUT: 0000-1111 (0-F) CLK: Clock cycle CLR: reset output to 0000 Cp: (PC) (PC)+1 Ep: output (PC)
D[0..3]

U1
D0 D1 D2 D3 CLK UCLK DCLK CNTUP OE CE LOAD RESET COUNTER_4 Q0 Q1 Q2 Q3 MIN MAX RCO D0 D1 D2 D3

Ep Cp CLR

Cp CLK CLR Ep
Program Counter (PC) 4

MAR

QL Q0 Q1 Q2 Q3 QU

INPUT: 8 bits (cccc oooo) OUTPUT: 4 bits (cccc) CLK: Clock cycle Lm: (MAR) input output HiByte(MAR)

D[0..3]

U2
D0 D1 D2 D3 DL D0 D1 D2 D3 DU CLK RESET HOLD UP LOAD OE SHIFTREG_4

CLK

Q[0..3]

Lm CLK
(Memory Address Register) MAR 8

Lm

ROM (R)
INPUT: 4 bits (cccc) OUTPUT: 8 bits (dddd dddd) Er: R input output (R)
A[0..3] D[0..7]

U3
A0 A1 A2 A3 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 CS WR RD MEMORY_12_8 FILE=PROM.BIN,ASCHEX D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7

Vcc

Er

16x8 PROM

Er

B,O Register (tri-state)

8

Lb

U51
X[0..7] D[0..7] DL D0 D1 D2 D3 D4 D5 D6 D7 DU CLK CLR CLK RESET HOLD UP LOAD OE SHIFTREG_8_BUS Y[0..7] Q[0..7] QL Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 QU

B register

CLK

INPUT: 8 bits (dddd dddd) OUTPUT: 8 bits (dddd dddd) CLK: Clock cycle
Lx: Load data in (A) input Ex: Enable data out output (A)

Li Ei

I Register
INPUT: 8 bits OUTPUT1: 8 bits

For ALU, direct output

For BUS, control by Ea

Li CLK CLR Ei
Instruction Register (IR)

OUTPUT2: 8 bits CLK: Clock cycle La: Load data in (A) input Ea: Enable data out output2 (A)

INPUT: 8 bits (cccc dddd) OUTPUT1: 4 bits (cccc)

For instruction decoder, direct output For BUS, control by Ei

OUTPUT2: 4 bits (dddd) CLK: Clock cycle

8 A register 8

La CLK Ea

Li: Load data in (IR) input Ei: Enable data out output2 (IR)

ALU
INPUT1: 8 bits (aaaa aaaa) INPUT2: 8 bits (bbbb bbbb) OUTPUT: 8 bits (dddd dddd) Su: Load data in 0 additional
(ALU)input1+input2 (ALU)input1-input2

Binary Display
INPUT: 8 bits (aaaa aaaa)

1 subtraction

Eu: Enable data out output (ALU)

8
8

Su
8 Arithmetic Logic Unit ALU
Binary Display D

Eu
8

Control Unit (CON)

RC
CLK CLR CLK CLR

COMPONENTS
Ring Counter

T0 T5
6 op-code signals 12 control signals

Instruction Decoder Control Matrix

I[4..7]

T[0..5] RING COUNTER

ID
I7 I6 I5 I4 I7 I6 I5 I4 LDA ADD SUB OUT HLT

CM
LDA ADD SUB OUT Lo Lb Eu Su Ea La Ei Li Er Lm Ep Cp Lo Lb Eu Su Ea La Ei Li Er Lm Ep Cp

INSTRUCTION DECODER

T[0..5]

CONTROL MATRIX HLT

CLOCK
Press START to begin
Generate CLK Generate CLR Reset system to Initial state

HLT Signal

Vcc

CLOCK(CLK1)

U0 11
CK L1 CK L AN D

START

CLOCK
CLK1 CLK START1 CLR START2
HT L CR L1

U9 1
CLK CLR
S AR 1 T T S AR 2 T T J K ST E RS T EE CK L J FF K Q !Q

U0 2
J K ST E RS T EE CK L J FF K Q !Q CR L

CLR1

HLT

CLOCK GENERATOR

OPCODE
LDA (0000 oooo)
0000 1001 = LDA (R9)
(A) (R9)
PROGRAM/DATA MEMORY R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 RA RB RC RD RE RF 0000 0001 0001 0001 0010 1110 1111 xxxx xxxx 0001 0001 0001 0001 0010 xxxx xxxx 1001 1010 1011 1100 1101 xxxx xxxx xxxx xxxx 0000 0100 1000 1100 0000 xxxx xxxx (LDA (ADD (ADD (ADD (SUB (ADD (ADD R9) RA) RB) RC) RD) RA) RA)

ADD (1111 oooo)

0001 1010 = ADD (RA)
(B) (RA) (A) (A)+(B)

SUB (0010 oooo)

0010 1100 = SUB (RC)
(B) (RC) (A) (A) (B)

(16) (20) (24) (28) (32)

OUT (1100 xxxx)

1100 xxxx = OUT
(D) <- (A)

HLT (1111 xxxx)

1111 xxxx = HLT

Ring Counter
CLK T0 T1 T2 T3 T4 T5

T0

R C
T1

T2

C LK C LR

C LK C LR

T3

T4

T[0..5 ] R GC U TE IN O N R

T5

Machine Cycle
CLK

T0

T1

T2

T3

T4

T5

Fetch Cycle Machine Cycle

Execute Cycle

Fetch Cycle (T0-T2) Execute Cycle (T3-T5)

Fetch Cycle
T0
EpLm CON (MAR) (PC)

T1
ErLi CON (IR) (RMAR)

T2
Cp CON (PC) (PC)+1

Execute Cycle
LDA
T3
LmEi CON (MAR) (oooo)

ADD
T3
LmEi CON (MAR) (oooo)

T4
ErLa CON (A) (Roooo)

T4
ErLb CON (B) (Roooo)

T5
No op

T5
LaEu CON (ALU) (A)+(B) (A) (ALU)

Execute Cycle
SUB
T3
LmEi CON (MAR) (oooo)

OUT
T3
EaLo CON (O) (A)

T4
ErLb CON (B) (Roooo)

T4
No Op

T5
LaSuEu CON (ALU) (A)+(B) (A) (ALU)

T5
No Op

HLT
T3
HLT signal

CONTROL UNIT (CON)

CLOCK CONTROL
CLK

HLT

CLR

Ring Counter
Instruction

Instruction decoder

Control Matrix

CON

12

Instruction Decoder
I7 I6 I5 I4

U4
NOT

U5
NOT

U6
NOT

U7
NOT

U8
LDA AND_4

U9
ADD AND_4

U10
SUB AND_4

U11
OUT AND_4

U12
HLT AND_4

CONTROL MATRIX
T .5 [ .] 0
T0 T1 T2 T3 T4 T5

LA D AD D SB U OT U

U3 U4 2 2
AD N AD N

U6 U7 2 2
AD N AD N

U9 U0 U1 2 3 3
AD N AD N AD N

U3 U4 3 3
AD N AD N

U6 U7 3 3
AD N AD N

U0 4
O_ R 4

U1 4
O_ R 4

U2 4
O_ R 3

U3 4
O_ R 3

U4 4
O R

U5 4
O R

Li

Cp

Ep

Er

Ei

La

Ea

Su

Eu

Lb

Lm

Ld

Operation sample
Press start button (PC) 0000 Start LDA R9 (MAR) (PC) R(MAR) 0000 1001 IR 0000 1001 (PC) (PC)+1 (MAR) IR(low) (A) R(MAR) NOOP ADD RA (MAR) (PC) R(MAR) 0001 1010 IR 0001 1010 (PC) (PC)+1 (MAR) IR(low) (B) R(MAR) (A) (A)+(B) ADD RB . . . PROGRAM/DATA MEMORY R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 RA RB RC RD RE RF 0000 0001 0001 0001 0010 1110 1111 xxxx xxxx 0001 0001 0001 0001 0010 xxxx xxxx 1001 1010 1011 1100 1101 xxxx xxxx xxxx xxxx 0000 0100 1000 1100 0000 xxxx xxxx (LDA (ADD (ADD (ADD (SUB (ADD (ADD R9) RA) RB) RC) RD) RA) RA) fetch TO fetch T1 fetch T2 exec T3 exec T4 exec T5 (MAR)= 0000 (R) = (R0) (PC) = 0001 (MAR)= 1001 (A) = (R9)

fetch TO fetch T1 fetch T2 exec T3 exec T4 exec T5

(MAR)= 0001 (R)= (R1) (PC) = 0010 (MAR)= 1010 (B)= (RA) (A)= 16+20

(16) (20) (24) (28) (32)