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1)
X
starea
actual
Q
starea
actual
starea
urmtoare
intrarea
Logica
strii
urmtoare
( CLC )
Q+
Registrul
de
stare
(memorie)
Q+ = f(X,Q)
Logica ieirea
de
Y
ieire
( CLC )
Y = g(Q)
clk
- intrarea X
- ieirea Y
Specificarea automatului
:
- strile
(variabilele de stare) Q
- funcia strii urmtoare Q+ = f(X,Q)
- funcia ieirii (tip Moore) Y = g(Q)
condiii de
meninere
a strii
starea
=> ieirea Y
Q = 0100
condiii de
tranziie
starea
ieirea Y <=
Q = 1010
port I/O
initializare
fisa
coca
pepsi
clk
iesire_coca
prezeta_coca
prezeta_pepsi
iesire_pepsi
iesire_fisa
fisa =
0
asteptare
fisa = 1
iesire_coca = 0
iesire_pepsi = 0
iesire_fisa = 0
pepsi = 1
control
coca
livrare
coca
iesire_coca = 1
iesire_pepsi = 0
iesire_fisa = 0
coca = 0
pepsi = 0
decizie
coca = 1
prezenta_coca
=1
iesire_coca = 0
iesire_pepsi = 0
iesire_fisa = 0
iesire_coca = 0
iesire_pepsi = 0
iesire_fisa = 0
control
pepsi
prezenta_coca
=0
prezenta_pepsi
=1
prezenta_pepsi
=0
restituire
fisa
iesire_coca = 0
iesire_pepsi = 0
iesire_fisa = 1
livrare
pepsi
iesire_coca = 0
iesire_pepsi = 1
iesire_fisa = 0
Structura
sursei VHDL :
Declararea portului :
entity AUTOMAT is
port ( fisa , coca , pepsi , clk, initializare,
prezenta_coca , prezenta_pepsi : in std_logic ;
iesire_coca , iesire_pepsi , iesire_fisa : out std_logic ) ;
end AUTOMAT ;
Descrierea arhitecturii :
begin
--Se transpune n cod VHDL diagrama strilor, folsind instruciuni
secveniale, n cadrul unui proces senzitiv la clk i la iniializare:
--
if - then - else
end process ;
--Se definesc ieirile asociate strilor,
folosind
instruciuni concurente when-else sau
with-select;
end arch_AUTOMAT
Declararea portului :
library ieee ;
use ieee.std_logic_1164.all ;
entity AUTOMAT is
port( fisa , coca , pepsi , clk, initializare
control_coca, control_pepsi : in std_logic ;
iesire_coca , iesire_pepsi , iesire_fisa : out std_logic ) ;
end AUTOMAT ;
Declararea strilor :
--multimea starilor
--starea curent
--initializare asincrona
sincronizare pe clk
case stare_actuala is
descrierea grafului starilor
when asteptare => if fisa = '1' then
stare_actuala <= decizie ;
else stare_actuala <= asteptare ; instructiune redundanta
end if ;
when decizie => if coca = '1' then
stare_actuala <= control_coca ;
elsif pepsi = '1' then
stare_actuala <= control_pepsi ;
else stare_actuala <= decizie ;
end if ;
when control_coca => if prezenta_coca = '1' then
stare_actuala <= livrare_coca;
else stare_actuala <= restituire_fisa ;
end if ;
Exemplu :
controller memorie
adresa
ready
Controller
r_w
clk
re
we
RAM
date
intrri
clk
t
ready
t
ieiri
r_w
re
t
we
t
ateptare decizie
citire
ateptare
decizie
scriere
ateptare
ready = 0
asteptare
S1
re = 0
we = 0
r_
w
rea
dy
=
scriere
S4
ready = 0
re = 0
we = 1
r_
w
=1
decizie
S2
re = 0
we = 0
y
read
ready = 1
citire
re = 1
we = 0
S3
ready = 0
library ieee ;
use ieee.std_logic_1164.all ;
entity CONTROLER is
port ( ready , r_w , clk : in std_logic ;
re , we : out std_logic ) ;
end CONTROLER ;
architecture arch_CONTROLER of CONTROLER is
type STARE is ( S1, S2, S3, S4 ) ;
signal S : STARE ;
begin
mulimea strilor
starea curent
begin
process (clk)
begin
if clkevent and clk=1 then
case S
is
diagrama strilor
S <= S2 ;
S <= S3 ;
S <= S4 ;
S <= S1 ;
S <= S1 ;
generarea iesirii
--cu instruciuni concurente
Primul proces :
starea_actual
i
starea_urmtoare
library ieee ;
use ieee.std_logic_1164.all ;
entity CONTROLER is port
( ready , r_w , clk : std_logic ;
re , we : out std_logic ) ;
end CONTROLER ;
architecture arch_CONTROLER of CONTROLER is
type STARE is ( S1, S2, S3, S4 ) ;
signal stare_actuala, stare_urmatoare : STARE ;
begin
mulimea strilor
stri curente
begin
-- diagrama strilor
case stare_actuala is
when S1 => if ready = '1' then stare_urmatoare <= S2 ; end if ;
when S2 => if r_w = '1'
then
else
when S3 => if ready = '1' then
when S4 => if ready = '1' then
stare_urmatoare <= S3 ;
stare_urmatoare <= S4 ; end if ;
stare_urmatoare <= S1 ; end if ;
stare_urmatoare <= S1 ; end if ;
end case ;
end process TRANZITII ;
SINCRONIZARE: process (clk)
proces care descrie sincronizarea pe clk
begin
if clkevent and clk=1 then
stare_actuala <= stare_urmatoare ;
end if ;
end process SINCRONIZARE ;
re <= 1 when stare_actuala = S3 else
0 ;
we <= 1 when stare_actuala = S4 else
--generarea iesirii
starea
urmtoare
intrare
Logica
strii
urmtoare
X
Q
( CLC1 )
starea
actual
Q (Q,X)
Q+
starea
actual
Registru
de
stare
( memorie )
ieire
Logica
de
ieire
( CLC2 )
Y(Q)
clk
x [1:0]
Logica
+
q
strii
urmtoare
CLC1
Registru
de
stare
(memorie)
Logica
de
ieire
CLC2
clk
y[2:0]
Diagrama strilor :
x "10"
S0
y = "000"
x
=
"1
0"
y = "111"
S3
S1
1"
"1
x=
"1
0
"
x = "11"
S2
y = "010"
x "11"
x "11"
x "10"
y = "101"
library ieee ;
use ieee.std_logic_1164.all ;
entity AUTOMAT is
port ( x : in std_logic_vector(1 downto 0) ;
clk : in std_logic ;
y : out std_logic_vector(2 downto 0) ) ;
end AUTOMAT ;
architecture arch_AUTOMAT of AUTOMAT is
type STARE is ( S0 , S1 , S2 , S3 ) ;
-- mulimea
strilor
signal S : STARE ;
begin
--starea curent
-- proces ce descrie
-- diagrama strilor
X
intrare
Logica
strii
urmtoare
Logica
de
ieire
+
Y(Q
)
Registru
de
starea
stare
urmtoare
Q+
clk
Y
ieire
Q
starea
actual
Exemplu :
INIT
INIT
y = "000"
(asincron)
S0
x=
x = "11"
S2
clk
y = "010"
"
"01
"0 0
"
x=
y [2:0]
x [1:0]
S1
x = "10"
y = "101"
--stri curente
case starea_actuala is
when S0 => if x = "01" then
starea_urmatoare <= S1 ;
end if ;
when S1 => if x = "11" then
starea_urmatoare <=S2 ;
end if ;
when S2 => if x = "00" then
starea_urmatoare <= S0 ;
elsif x = "10" then
starea_urmatoare <= S1 ;
end if ;
end case ;
end process proc_AUTOMAT ;
--descrie diagrama
S0 ,
"101" when
S1 ,
"010" when
others ;
--iniializeaz
automatul
--sincronizeaz tranziiile cu
b)
intrare
Q
starea
actual
Logica
strii
urmtoare
i a ieirii
Q+(Q,X)
Y(Q+)
ieire
Q+
starea
urmtoare
Registru de
stare
Q
starea
actual
clk
library ieee ;
use ieee.std_logic_1164.all ;
entity AUTOMAT is
port ( INIT, clk : in std_logic ;
x : in std_logic_vector (1 downto 0) ;
y : out std_logic_vector (2 downto 0) ) ;
end AUTOMAT ;
architecture arch_AUTOMAT of AUTOMAT is
type STARE is (S0, S1, S2) ;
signal starea_actuala, starea_urmatoare : STARE
begin
--mulimea strilor
--stri curente
descrie tranziiile
i asociaz ieirea y cu starea urmtoare
case starea_actual is
when S0 =>
y <="101" ;
y <="010" ;
iniializare i sincronizare
3)
starea
urmtoare
intrare
Logica
strii
urmtoare
X
Q
( CLC )
Q+
starea
actual
Registru
de
stare
i
ieire
clk
( memori
e)
ieire
Q
Y
RESET
asincron
S0
y [1:0]
q = "000"
reset
"
"10
x=
x=
"01
"
clk
y = "00"
x = "00"
S4
S1
y = "10"
y = "01"
q = "010"
"0
1"
q = "101"
=
x
11"
x="
S3
y = "00"
x = "1
1"
x [1:0]
S2
y = "11"
q = "100"
x = "00"
q = "011"
library ieee ;
use ieee.std_logic_1164.all ;
entity AUTOMAT is port
(RESET, clk : in std_logic ;
x : in std_logic_vector(1 downto 0) ;
y : buffer std_logic_vector(1 downto 0) ) ;
end AUTOMAT ;
architecture arch_AUTOMAT of AUTOMAT is
signal S : std_logic_vector(2 downto 0) ;
-starea curent
:=
:=
:=
:=
:=
"000" ;
"010" ;
"011" ;
"100" ;
"101" ;
end arch_AUTOMAT ;
4)
(Logica de ieire este asemntoare cu a unui un codificator zecimal/binar, avnd o singur intrare
Registrul de
stare
qn-1
X
intrare
Q
starea
actual
Logica
Q+
strii
urmtoare
starea
( CLC1 )
Logica
de
ieire
( CLC2 )
..
.
q2
q1
urmtoare
q0
Q+(Q,X)
Y(Q)
clk
Q
starea
actual
Y
ieire
S0
S1
S2
.
.
.
Sn-2
Sn-1
qn-1 qn-2
Q
q 3 q2
0
0
0
0
0
0
0
1
1
0
q1
q0
0
0
0
0 0
0 1
1 0
1
0
0
0
0
0
0
0
0
0
0
Exemplu :
INIT
INIT
asincron
S0
y [1:0]
y = "00"
q = "00001"
"10
x=
x=
"01
"
x [1:0]
"
clk
x = "00"
S3
S1
q = "10000"
q = "00010"
"0
x
11"
x="
y = "00"
x = "1
1"
1"
y = "01"
y = "10"
S3
S2
q = "01000"
q = "00100"
x = "00"
y = "11"
Descrierea VHDL :
-directiva de sintez care foreaz o implementare de tip "one-hot-one" :
attribute
library ieee ;
use ieee.std_logic_1164.all ;
entity AUTOMAT is port
(clk , INIT : in std_logic ;
x : in std_logic_vector(1 downto 0) ;
y : out std_logic_vector(1 downto 0) ) ;
end AUTOMAT ;
architecture arch_AUTOMAT of AUTOMAT is
type STARE is (S0, S1, S2, S3, S4) ;
attribute state_encoding of STARE : type is one_hot_one ;
signal S : STARE ;
begin
begin
if INIT = '1' then S <= S0 ;
elsif (clk'event and clk='1') then
case S is when S0 => if x="10" then S<=S1 ; end if ;
when S1 => if x="00" then S<=S4 ;
elsif x="11" then S<=S2 ; end if ;
when S2 => if x="00" then S<=S3 ; end if ;
when S3 => if x="01" then S=S1 ;
elsif x="11" then S<=S4 ; end if ;
when S4 => if x="01 then S<=S0 ; end if ;
end case ;
end if ;
end process proc_AUTOMAT ;
y <= "00" when (S = S0 or S = S3) else
"10" when (S = S1 ) else
"11" when (S = S2) else
"01" ;
end arch_automat ;
--genereaz ieirea y
y = "00"
"10
x=
S0
q= "000"
x=
"01
"
Ex. :
"
Tabelul tranziiilor :
S2
S3
q= "100"
q= "011"
x = "00"
Starea actual
nume cod (q)
S0
000
S1
010
S2
S3
011
100
S4
101
y = "10"
x = "1
1"
"0
1"
S1
q= "010"
11"
x="
y = "00"
x = "00"
y = "01"
S4
q= "101"
Intrarea
x
10
11
00
00
01
11
01
y = "11"
Starea urmtoare
nume cod (q+)
S1
010
S2
011
S4
101
S3
100
S1
010
S4
101
S0
000
library ieee ;
use ieee.std_logic_1164.all ;
use work.table_std.all ;
tablouri
entity AUTOMAT is
port (clk , INIT : in std_logic ;
x : in std_logic_vector(1 downto 0) ;
y : out std_logic_vector(1 downto 0) ) ;
end AUTOMAT ;
--denumirile i
--codurile strilor
--starea actual
intrarea
starea urmtoare
ieirea
----------------------------------------------------------------
S0
&
"10"
&
S1
S1
S2
S3
S3
S4
&
&
&
&
&
&
"11" &
"00" &
"00" &
"01" &
"11" &
"01" &
S1
&
S2
S4
S3
S1
S4
S0
&
&
&
&
&
&
"10" ,
--tabelul
tranziiilor
"11"
"01"
"00"
"10"
"01
"00"
,
,
,
,
,
);
--& : operator concatenare
begin
--iniializare
--cod stare = "000" , ieire = "00"
--sincronizare pe front
cresctor
iesire _tabel <= ttf ( TABEL , S & x ) ;
--extrage o linie de tablou i o atribuie variabilei
"iesire_tabel"
end if ;
-- generarea strii urmtoare i a ieirii :
end process ;
S <= iesire_tabel (0 to 2) ;
--extrage codul strii curente din variabila "ieire_tabel"
y <= iesire_tabel ( 3 to 4 ) ;
end arch_AUTOMAT ;
work.table_std .
starea
urmtoare
intrare
X
starea
actual
Logica
strii
Q+
urmtoare
( CLC )
Registrul
de
stare
starea
actual
( memorie )
Q+ = f(Q,X)
ieire
clk
Q
X
Logica
de
ieire
)
Y( =CLC
f(Q,X)
Descrierea automatului :
- Evoluia strilor se descrie n cadrul unui proces
(ca n cazul automatelor Moore).
Exemplu :
S1
x=
"01
"
S4
"
x = "11
y = "11" dac x =
11
y = 10 dac x =
01
y = 00 dac x
11
i x
01
"1
0"
INIT
( asincron)
y = 11 dac x =
00
y = 00 dac x
00
x=
S0
"1
0"
y = "11"
S3
S2
x = "00"
y = "01" dac x = 00
y = "11" dac x = 11
y = 00 dac x 00
i x 11
y = "01"
library ieee ;
use ieee.std_logic_1164.all ;
entity MEALY is port
(x
: in std_logic_vector (1 downto 0) ;
clk, INIT : in std_logic ;
y
: out std_logic_vector (1 downto 0) ) ;
end MEALY ;
architecture arch_MEALY of MEALY is
type STARE is ( S0 , S1 , S2 , S3 , S4 ) ;
signal S : STARE ;
begin