Proiect Soc@

Proiect
Structura si organizarea calculatoarelor 2
Profesor Proiect: Ionescu Laurentiu
Profesor Laborator: Mazare Alin
Profesor Curs: Serban Gheorghe
Student: Potirniche Florian Alexandru
Anul: III
Grupa: 2
Subgrupa: 2
Detalii proiect:
Se da urmatorul set de instructiuni: A (AL3,AI5,AL7,AL10,M1,M2,J2,J3,J5)
Aceste instructiuni se aplica asupra unor registrii de uz general, reprezentati generic cu Rd si Rs.
La realizarea programelor, d si s se inlocuiesc cu numere incepand cu valorea 0, deci vom avea
R0,R1,etc.
Numarul de registriii (deci valorile maxime posibile pentru d si s) este: B (19)
Instructiunile vor avea ca operanzi registrii (deci vor opera asupra continutului lor), constant
(reprezentate cu ct – reprezinta valori numerice date din memoria de date sau adrese de memorie date.
Dimensiunea acestora este de: C (19) biti.
Se cere:
a) Sa se proiecteze toate structurile hardware necesare pentru a implenta instructiunile de mai

sus.
b) Utilizand instructiunile de mai sus sa se realizeze un program care sa efectueze urmatoarele:
Se dau D (19) numere care se afla depuse in memoria de date, incepand cu o adresa aleasa de
proiectant. Sa se efectueze o operatie E (AL3) intre toti termenii iar rezultatul(sau rezultatele) sa se
depuna in memoria de date la o adresa de asemenea stabilita de proiectant dar care nu se
suprapune cu cea in care se afla termenii initiali.
-AL3 => AND Rd, Rs1, Rs2 => In registrul Rd se plaseaza rezultatul SI logic dintre
continutul registrului Rs1 si Rs2
Cod VHDL:
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity AL3 is
port(
a : in STD_LOGIC_VECTOR(18 downto 0);
b : in STD_LOGIC_VECTOR(18 downto 0);
c : out STD_LOGIC_VECTOR(18 downto 0)
);
end AL3;
architecture AL3a of AL3 is
begin
c<=a AND b;
end AL3a;
-AI5 => XRI Rd, Rs, Ct => In registrul Rd se plaseaza rezultatul SAU exclusiv
logic dintre continutul registrului Rs1 si ct
Cod VHDL:
library IEEE;
entity AI5 is
port(
Rs : in STD_LOGIC_VECTOR(18 downto 0);
Rd : out STD_LOGIC_VECTOR(18 downto 0)

);
end AI5;
architecture AI5a of AI5 is
begin
Rd<=Rs XOR "011000011101011101";
end AI5a;
AL7 => MUL Rd1,Rd2,Rs1,Rs2 => In registrul Rd1 se plaseaza partea High si in
registrul Rd2 se plaseaza partea Low din produsul dintre continutul registrului
Rs1 si Rs2
-AL10 => SR Rd,Rs => In registrul Rd se plaseaza rezultatul deplasarii cu o poz la
dreapta a continutului registrului Rs, bitul High este 0\
Cod VHDL:
library IEEE;
entity AL10 is
port(
operator : in STD_LOGIC_VECTOR(18 downto 0);
iesire : out STD_LOGIC_VECTOR(18 downto 0)
);
end AL10;
architecture AL10a of AL10 is
signal operator_intermediar: std_logic_vector(18 downto 0);
begin
operator_intermediar(18 downto 1) <= operator(17 downto 0);
operator_intermediar(0) <= '0';
iesire <= operator_intermediar;
end AL10a;
M1 => SV (Rd),Rs => Este salvata (scrisa) in memoria de date la adresa

continuta in registrul Rd data continuta in registrul Rs
M2 => LD Rd,(Rs) => Este preluata (citita) din memoria de date de la adresa
continuta in registrul Rs o data care este depusa in registrul Rd
J2 => JPZ adr => salt la adresa adr (val absoluta) daca indicatorul Zero este 1
J3 => JPNC adr => salt la adresa adr(val absoluta) daca indicatorul Carry este 0
J5 => JPNZ adr => salt la adresa adr(val absoluta) daca indicatorul Zero este 0
Circuit zero:
library IEEE;
use IEEE.STD_logic_1164.all;
entity circuit_zero is
port(
i : in std_logic_vector(18 downto 0);
rez : out std_logic
);
end circuit_zero;
architecture circuit_zero_a of circuit_zero is
begin
rez<= i(0) or i(1) or i(2) or i(3) or i(4) or i(5) or i(6) or i(7) or i(8) or i(9) or i(10)
or i(11) or i(12) or i(13) or i(14) or i(15) or i(16) or i(17) or i(18);
end circuit_zero_a;
Dmux 1:16 :
library IEEE;
entity dmux1_16 is
port(
E : in STD_LOGIC;
s : in STD_LOGIC_VECTOR(3 downto 0);
y0 : out STD_LOGIC;
y1 : out STD_LOGIC;
y2 : out STD_LOGIC;
y3 : out STD_LOGIC;
y4 : out STD_LOGIC;
y5 : out STD_LOGIC;
y6 : out STD_LOGIC;
y7 : out STD_LOGIC;
y8 : out STD_LOGIC;
y9 : out STD_LOGIC;
y10 : out STD_LOGIC;
y15 : out STD_LOGIC
);
end dmux1_16;
architecture dmux_16a of dmux1_16 is
begin
process(s)
begin
if(s="0000")then
y0<=E;
elsif(s="0001")then
y1<=E;
elsif(s="0010")then
y2<=E;
elsif(s="0011")then
y3<=E;
elsif(s="0100")then
y4<=E;
elsif(s="0101")then
y5<=E;
elsif(s="0110")then
y6<=E;
elsif(s="0111")then
y7<=E;
elsif(s="1000")then
y8<=E;
elsif(s="1001")then
y9<=E;
elsif(s="1010")then
y10<=E;
elsif(s="1011")then
y11<=E;
elsif(s="1100")then
y12<=E;
elsif(s="1101")then
y13<=E;
elsif(s="1110")then
y14<=E;
elsif(s="1111")then
y15<=E;
end if;
end process;
end dmux_16a;
Mux 4:1 :
library IEEE;
entity mux4_1 is
port(
I0 : in STD_LOGIC;
I1 : in STD_LOGIC;
I2 : in STD_LOGIC;
I3 : in STD_LOGIC;
S0 : in STD_LOGIC;
S1 : in STD_LOGIC;
Z : out STD_LOGIC
);
end mux4_1;
architecture mux4_1_a of mux4_1 is
begin
process (I0,I1,I2,I3,S0,S1) is
begin
if (S0 ='0' and S1 = '0') then
Z <= I0;
elsif (S0 ='1' and S1 = '0') then
Z <= I1;
elsif (S0 ='0' and S1 = '1') then
Z <= I2;
else
Z <= I3;
end if;
end process;
end mux4_1_a;
Mux 19:1 :
library IEEE;
entity mux19_1 is
port(
x0 : in STD_LOGIC_VECTOR(18 downto 0);
s : in STD_LOGIC_VECTOR(4 downto 0);
y : out STD_LOGIC_VECTOR(18 downto 0);
x18 : in STD_LOGIC_VECTOR(18 downto 0)
);
end mux19_1;
architecture mux_19_1a of mux19_1 is

begin
process(x0,x1,x2,x3,x4,x5,x6,x7,x8,x9,x10,x11,x12,x13,x14,x15,x16,x17,x18,s)
begin
if(s="00000")then
y<=x0;
elsif(s="00001")then
y<=x1;
y<=x2;
y<=x3;
y<=x4;
y<=x5;
y<=x6;
y<=x7;
y<=x8;
y<=x9;
y<=x10;
y<=x11;
y<=x12;
y<=x13;
y<=x14;
y<=x15;
y<=x16;
y<=x17;
y<=x18;
else
y<="ZZZZZZZZZZZZZZZZZZZ";
end if;
end process;
end mux_19_1a;
RPP:
Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity rpp is
port(
clk: in std_logic;
di: in std_logic_vector(18 downto 0);
q: out std_logic_vector(18 downto 0)
);
end rpp;
architecture rpp_a of rpp is
begin
process(clk,di)
begin
if clk'event and clk='1' then
q<=di;
end if;
end process;
end rpp_a;
Sumator 19 biti:
library IEEE;
use IEEE.std_logic_1164.all;
entity sumator19bit is
port(
a19 : in STD_LOGIC_vector(18 downto 0);

b19 : in STD_LOGIC_vector(18 downto 0);
co_fin : out STD_LOGIC;
s19 : out STD_LOGIC_vector(18 downto 0)
);
end sumator19bit;
architecture sumator19bit_a of sumator19bit is
component sumator1bit
port (
a : in STD_LOGIC;
b : in STD_LOGIC;
ci : in STD_LOGIC;
co : out STD_LOGIC;
s : out STD_LOGIC
);
end component;
constant Ground : STD_LOGIC := '0';
signal GND : STD_LOGIC;
signal co1,co2,co3,co4,co5,co6,co7,co8,co9,co10,co11,co12,co13,co14,co15,co16,co17,co18 :
STD_LOGIC;
begin
U1 : sumator1bit
port map(
a => a19(0),
b => b19(0),
ci => GND,
co => co1,
s => s19(0)
);
U2 : sumator1bit
port map(
a => a19(1),
b => b19(1),
ci => co1,
co => co2,
s => s19(1)
);
U3 : sumator1bit
port map(
a => a19(2),
b => b19(2),
ci => co2,
co => co3,
s => s19(2)
);
U4 : sumator1bit
port map(
a => a19(3),
b => b19(3),
ci => co3,
co => co4,
s => s19(3)
);
U5 : sumator1bit
port map(
a => a19(4),
b => b19(4),
ci => co4,
co => co5,
s => s19(4)
);
U6 : sumator1bit
port map(
a => a19(5),
b => b19(5),
ci => co5,
co => co6,
s => s19(5)
);
U7 : sumator1bit
port map(
a => a19(6),
b => b19(6),
ci => co6,
co => co7,
s => s19(6)
);
U8 : sumator1bit
port map(
a => a19(7),
b => b19(7),
ci => co7,
co => co8,
s => s19(7)
);
U9 : sumator1bit
port map(
a => a19(8),
b => b19(8),
ci => co8,
co => co9,
s => s19(8)
);
U10 : sumator1bit
port map(
a => a19(9),
b => b19(9),
ci => co9,
co => co10,
s => s19(9)
);
U11 : sumator1bit
port map(
a => a19(10),
b => b19(10),
ci => co10,
co => co11,
s => s19(10)
);
U12 : sumator1bit
port map(
a => a19(11),
b => b19(11),
ci => co11,
co => co12,
s => s19(11)
);
U13 : sumator1bit
port map(
a => a19(12),
b => b19(12),
ci => co12,
co => co13,
s => s19(12)
);
U14 : sumator1bit
port map(
a => a19(13),
b => b19(13),
ci => co13,
co => co14,
s => s19(13)
);
U15 : sumator1bit
port map(
a => a19(14),
b => b19(14),
ci => co14,
co => co15,
s => s19(14)
);
U16 : sumator1bit
port map(
a => a19(15),
b => b19(15),
ci => co15,
co => co16,
s => s19(15)
);
U17 : sumator1bit
port map(
a => a19(16),
b => b19(16),
ci => co16,
co => co17,
s => s19(16)
);
U18 : sumator1bit
port map(
a => a19(17),
b => b19(17),
ci => co17,
co => co18,
s => s19(17)
);
U19 : sumator1bit
port map(
a => a19(18),
b => b19(18),
ci => co18,
co => co_fin,
s => s19(18)
);
GND <= Ground;
end sumator19bit_a;
Sumator 1 bit:
library ieee;
use ieee.std_logic_1164.all;
entity sumator1bit is
port(
a: in std_logic;
b: in std_logic;
ci: in std_logic;
co: out std_logic;
s: out std_logic
);
end sumator1bit;
architecture sumator1bit_a of sumator1bit is
signal s1,t1,t2: std_logic;
begin
s1 <= a xor b;
t1 <= a and b;
s <= s1 xor ci;
t2 <= s1 and ci;
co <= t1 or t2;
end sumator1bit_a;
Schema UAL:
Rps19biti:
library IEEE;
use IEEE.std_logic_unsigned.all;
entity rps19biti is
port(
si : in STD_LOGIC;
s_notp : in STD_LOGIC;
clk : in STD_LOGIC;
pi : in STD_LOGIC_VECTOR(18 downto 0);

q : out STD_LOGIC_VECTOR(18 downto 0)
);
end rps19biti;
architecture rps19biti_a of rps19biti is
begin
process(clk,pi,si,s_notp)
variable q_int : std_logic_vector(18 downto 0);
begin
if clk'event and clk='1' then
if s_notp = '0' then
q_int := pi;
else
q_int(17 downto 0) := q_int(18 downto 1);
q_int(18) := si;
end if;
end if;
q <= q_int;
end process;
end rps19biti_a;
Schema registri:
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Proiect

Structura si organizarea calculatoarelor 2

Profesor Proiect: Ionescu Laurentiu

Profesor Laborator: Mazare Alin

Profesor Curs: Serban Gheorghe

Student: Potirniche Florian Alexandru

Numarul de registriii (deci valorile maxime posibile pentru d si s) este: B (19)

Dimensiunea acestora este de: C (19) biti.

a) Sa se proiecteze toate structurile hardware necesare pentru a implenta instructiunile de mai

a : in STD_LOGIC_VECTOR(18 downto 0);

b : in STD_LOGIC_VECTOR(18 downto 0);

c : out STD_LOGIC_VECTOR(18 downto 0)

architecture AL3a of AL3 is

Rs : in STD_LOGIC_VECTOR(18 downto 0);

Rd : out STD_LOGIC_VECTOR(18 downto 0)

architecture AI5a of AI5 is

Rd<=Rs XOR "011000011101011101";

operator : in STD_LOGIC_VECTOR(18 downto 0);

iesire : out STD_LOGIC_VECTOR(18 downto 0)

architecture AL10a of AL10 is

signal operator_intermediar: std_logic_vector(18 downto 0);

operator_intermediar(18 downto 1) <= operator(17 downto 0);

operator_intermediar(0) <= '0';

iesire <= operator_intermediar;

M1 => SV (Rd),Rs => Este salvata (scrisa) in memoria de date la adresa

i : in std_logic_vector(18 downto 0);

rez : out std_logic

architecture circuit_zero_a of circuit_zero is

or i(11) or i(12) or i(13) or i(14) or i(15) or i(16) or i(17) or i(18);

s : in STD_LOGIC_VECTOR(3 downto 0);

y10 : out STD_LOGIC;

y11 : out STD_LOGIC;

y12 : out STD_LOGIC;

y13 : out STD_LOGIC;

y14 : out STD_LOGIC;

y15 : out STD_LOGIC

architecture dmux_16a of dmux1_16 is

architecture mux4_1_a of mux4_1 is

elsif (S0 ='1' and S1 = '0') then

elsif (S0 ='0' and S1 = '1') then

x0 : in STD_LOGIC_VECTOR(18 downto 0);

x1 : in STD_LOGIC_VECTOR(18 downto 0);

x2 : in STD_LOGIC_VECTOR(18 downto 0);

x3 : in STD_LOGIC_VECTOR(18 downto 0);

x4 : in STD_LOGIC_VECTOR(18 downto 0);

x5 : in STD_LOGIC_VECTOR(18 downto 0);

x6 : in STD_LOGIC_VECTOR(18 downto 0);

x7 : in STD_LOGIC_VECTOR(18 downto 0);

x8 : in STD_LOGIC_VECTOR(18 downto 0);

x9 : in STD_LOGIC_VECTOR(18 downto 0);

x10 : in STD_LOGIC_VECTOR(18 downto 0);

x11 : in STD_LOGIC_VECTOR(18 downto 0);

x12 : in STD_LOGIC_VECTOR(18 downto 0);

x13 : in STD_LOGIC_VECTOR(18 downto 0);

x14 : in STD_LOGIC_VECTOR(18 downto 0);

x15 : in STD_LOGIC_VECTOR(18 downto 0);

x16 : in STD_LOGIC_VECTOR(18 downto 0);

x17 : in STD_LOGIC_VECTOR(18 downto 0);

s : in STD_LOGIC_VECTOR(4 downto 0);

y : out STD_LOGIC_VECTOR(18 downto 0);

x18 : in STD_LOGIC_VECTOR(18 downto 0)

architecture mux_19_1a of mux19_1 is

di: in std_logic_vector(18 downto 0);