Radiocomunicații: Oradea, 2020

Radiocomunicații
Oradea, 2020
Radiocomunicații
Semnificaţie Radiocomunicații Unde electromagnetice şi spectrul
De ce RF? Necesitatea utilizării electromagnetic.
radiocomunicaţiilor. - Câmpul electric şi câmpul magnetic.
- Comunicarea umană - Câmpul electromagnetic.
- Semnale în banda de bază – exemple - Ecuaţia undei plane – Helmholtz.
- Multiplexarea cu diviziune în timp - Spectrul electromagnetic.
TDM, multiplexarea cu diviziune în Sisteme de radio (RF) comunicaţii.
frecvenţă FDM - Componentele de bază ale unui sistem
- Transmiterea semnalelor vocale, a de radiocomunicaţii.
semnalelor video şi a datelor la - Antena.
distanţă cu ajutorul undelor radio Sistem de transmisie.
Sistem de recepţie.
Structuri de sisteme de comunicaţie.
Performanţele sistemelor de
comunicaţii.
Radiocomunicații
Semnificaţia termenului Radiofrecvenţă (RF) engl. Radio frequency
Definiţii
• Oricare dintre frecvenţele undelor electromagnetice cuprinse în domeniul
3 kHz până la aproximativ 300 GHz şi care include frecvenţele folosite
pentru semnale de comunicaţii (cum ar fi pentru radio şi televiziune şi
transmisiile cu telefoane mobile şi sateliţi) sau semnale Radar [1].
• Radiofrecvenţă - Frecvență a undelor electromagnetice care se folosesc în

radiocomunicații [2].
Radiocomunicații
Perioadă [s] – frecvenţă [Hz]

( timp )
f=1/T
Ex. 1 : Perioada tensiunii de la reţeaua electrică este de 20 ms. Frecvenţa

tensiunii de la reţea este de 50 Hz
Ex. 2: Un semnal cu frecvenţa de 300 MHz are perioada de 3,33 x e-9 s
Radiocomunicații
De ce RF?
Necesitatea utilizării radiocomunicaţiilor.
Radiocomunicații
Comunicarea umană.
Schimbul de informaţii între oameni folosind unde sonore / acustice. [3]

Radiocomunicații
Comunicarea umană.
Avantaje:
- Vorbirea este un mijloc de comunicare natural şi eficient pentru om.
- Poate transmite stări, emoţii, sentimente etc.
- Se pot transmite nuanţe, subînțelesuri etc.
- Se realizează cu precădere din direcţia gurii spre ascultător. Există o
anumită directivitate.
Radiocomunicații
Comunicarea umană.
Dezavantaje:
- Comunicarea este dificilă în alte limbi pe care nu le cunoaştem bine (se
completează eventual cu limbajul gestual).
- Viteză de transmitere a informaţiilor este infimă raportată la sistemele
moderne de transmisii de date.
- Distanţa de comunicare este mică (şoaptă câţiva centimetri, strigăt câteva
zeci de metri) de ex. şoaptă – posibilă neinteligibilitate, strigăt – efort,
consum de energie, oboseală, deranj etc.
- Semnalul vocal nu se transmite omnidirecţional cu aceeaşi intensitate.
- Pt. semnale cu intensitate redusă, pentru a auzi mai bine, ascultătorul îşi
întoarce capul cu urechea spre persoana care vorbeşte.
- Nu se poate vorbi simultan ci doar pe rând.
Radiocomunicații
Semnale în Banda de bază. Exemple de semnale în banda de bază.
Semnal audio (microfon –> semnal electric) reprezentare în domeniul timp
Spectrul semnalului audio – reprezentare în domeniul frecvenţă (la un moment dat)

Radiocomunicații
0
fmin fmax f
BB = fmax – f min
Radiocomunicații
Semnalul stereo
multiplex (semnal
provenit de la două
microfoane plasate
la o anumită
distanţă unul faţă
de altul). Spectrul
semnalului stereo.
[4]
la recepţie [5]
Radiocomunicații
[6], [7]
Radiocomunicații
Semnal video complex NTSC [8]

Radiocomunicații
Comunicaţii digitale
Radiocomunicații
Cu cât se transmite mai multă informaţie în

unitatea de timp, cu atât va fi mai mare
banda de bază a transmisiei respective.
Radiocomunicații
Multiplexarea cu diviziune în timp TDM,

multiplexarea cu diviziune în frecvenţă FDM
Radiocomunicații
Transmiterea semnalelor vocale, a semnalelor video şi a

datelor la distanţă cu ajutorul undelor radio
Radiocomunicații
Proprietăţile undelor radio / câmpurilor electromagnetice
•Undele radio se propagă, se răspândesc din aproape în aproape,
în spaţiu şi în timp cu o anumită viteză.
•În vid, undele radio se propagă cu viteza luminii 300000 Km/s.
În mediul înconjurător, viteza de propagare a undelor radio este mai mică.
(exemplu – o unda radio ar putea înconjura circumferinţa pământului la
ecuator de 7,5 ori într-o secundă).
•Propagarea undelor radio poate fi direcţionată sau se poate realiza pe mai
multe direcţii (chiar şi omnidirecţional).
•Pe măsură ce frontul de undă înaintează în spaţiu şi timp, intensitatea lui
scade invers proporţional cu distanţă sau pătratul distanţei faţă de locul de
generare / locul de radiaţie.
•Se pot realiza comunicaţii radio la scurtă şi foarte lungă distanţă
(chiar şi în spaţiul cosmic) fără a fi necesar un suport care să asigure
comunicaţia (de ex. cabluri etc.).
•Cum ne putem folosi de aceste proprietăţi?
Exemple: Transmisia cu undă continuă – CW; Radiodifuziunea; Televiziunea;
Radiocomunicaţiile profesionale; CB; Comunicaţiile mobile 2,5G – 5G;
Transmisii de date Wi-Fi (wireless local area network bazat pe standardele
IEEE 802.11) etc.
Radiocomunicații
Câmpul electric
Câmpul electric este generat de către sarcini electrice sau de către câmpuri
magnetice variabile. Pentru a vedea cum influenţează o cantitate de sarcină
electrică spaţiul din jurul acesteia se foloseşte noţiunea de câmp electric.
Câmpul electric este un câmp vectorial. În fiecare punct din spaţiu în care se
manifestă, câmpul electric are o mărime, direcţie şi sens. Liniile de câmp pot să
pornească dintr-un punct şi să ajungă într-un alt punct. Liniile de câmp pot fi
deschise. U.m. echivalentă este [V/m]. Electronul are o sarcină electrică (o cantitate
de electricitate) negativă egală cu 1,602·10-19 C (coulomb).
Linii de câmp electric

Radiocomunicații
E = kQ / d2 – (intensitatea) campul
electric la o distanţă d faţă de sarcina
Q
E = F/q – vectorul câmp electric

definit ca raportul dintre forţa F care
acţionează asupra unei sarcini de
test “q”.
Pe măsură ce distanţa creşte, scade forţa cu care acţionează sarcina Q

asupra sarcinii de test q. Dacă sarcinile electrice sunt de acelaşi semn
se atrag, altfel acestea se resping. Sarcina electrică se poate stoca, acumula.
Radiocomunicații
Radiocomunicații
Câmpul magnetic
Câmpul magnetic poate fi generat cu ajutorul unui curent electric (o

mişcare ordonată de electroni). Câmpul magnetic este un câmp vectorial.
În fiecare punct din spaţiu în care se manifestă, câmpul magnetic este
caracterizat de mărime, direcţie şi sens. Câmpul magnetic are linii de
câmp / linii de forţă închise. U.m. echivalentă este [A/m].
Linii de câmp magnetic

Radiocomunicații
B = μ0 I / 2πr – unde r este distanţa de la
conductorul parcurs de curentul I la punctul în
care se măsoară valoarea câmpului magnetic
iar μ0 reprezintă permeabilitatea vidului.
B reprezintă inducţia câmpului magnetic.

U.m. [T].
B = μ0 H unde H este intensitatea câmpului

magnetic.
Forţa lui Lorentz pentru o particulă încărcată electric cu sarcina q care se

deplasează cu viteza v într-un cîmp magnetic de inducţie B: F = qE + qv x B
Radiocomunicații
Câmpul electromagnetic
Câmpul electromagnetic este un câmp vectorial care combină un
câmp electric şi un câmp magnetic.
Comportamentul câmpului electromagnetic poate fi descris cu ajutorul

ecuaţiilor lui Maxwell:
1. ·E = ρ / ε0 Legea lui Gauss
2. ·B = 0 Legea lui Gauss pt. câmpuri magnetice
3.  x E = - B / t Legea lui Faraday
4.  x B = μ0J + μ0ε0 E / t Legea Maxwell-Ampère
unde ρ reprezintă densitatea de sarcină iar J este densitatea de curent.
Termenul μ0ε0 E / t pune în evidenţă curentul de deplasare.
Ec. 3 sugerează faptul că un câmp magnetic variabil generează un

câmp electric iar ec. 4 indică faptul că un curent electric variabil generează
un câmp magnetic.
a LF–2.7 GHz
RF/IF Gain and Phase Detector
AD8302
FEATURES FUNCTIONAL BLOCK DIAGRAM
Measures Gain/Loss and Phase up to 2.7 GHz
Dual Demodulating Log Amps and Phase Detector AD8302
Input Range –60 dBm to 0 dBm in a 50 ⍀ System MFLT
VIDEO OUTPUT – A + +
Accurate Gain Measurement Scaling (30 mV/dB) VMAG
– –
Typical Nonlinearity < 0.5 dB INPA 60dB LOG AMPS
(7 DETECTORS)
Accurate Phase Measurement Scaling (10 mV/Degree) OFSA
Typical Nonlinearity < 1 Degree

MSET
Measurement/Controller/Level Comparator Modes
Operates from Supply Voltages of 2.7 V–5.5 V COMM PHASE
DETECTOR
Stable 1.8 V Reference Voltage Output PSET
Small Signal Envelope Bandwidth from DC to 30 MHz
APPLICATIONS OFSB 60dB LOG AMPS –
RF/IF PA Linearization INPB (7 DETECTORS) VPHS
+
Precise RF Power Control VIDEO OUTPUT – B PFLT
Remote System Monitoring and Diagnostics 1.8V
Return Loss/VSWR Measurements VPOS BIAS x3 VREF
Log Ratio Function for AC Signals
PRODUCT DESCRIPTION The signal inputs are single-ended, allowing them to be matched
The AD8302 is a fully integrated system for measuring gain/loss and connected directly to a directional coupler. Their input
and phase in numerous receive, transmit, and instrumentation impedance is nominally 3 kΩ at low frequencies.
applications. It requires few external components and a single The AD8302 includes a phase detector of the multiplier type,
supply of 2.7 V–5.5 V. The ac-coupled input signals can range but with precise phase balance driven by the fully limited signals
from –60 dBm to 0 dBm in a 50 Ω system, from low frequencies appearing at the outputs of the two logarithmic amplifiers.
up to 2.7 GHz. The outputs provide an accurate measurement Thus, the phase accuracy measurement is independent of signal
of either gain or loss over a ± 30 dB range scaled to 30 mV/dB, level over a wide range.
and of phase over a 0°–180° range scaled to 10 mV/degree.
Both subsystems have an output bandwidth of 30 MHz, which The phase and gain output voltages are simultaneously available
may optionally be reduced by the addition of external filter at loadable ground referenced outputs over the standard output
capacitors. The AD8302 can be used in controller mode to range of 0 V to 1.8 V. The output drivers can source or sink up
force the gain and phase of a signal chain toward predetermined to 8 mA. A loadable, stable reference voltage of 1.8 V is avail-
setpoints. able for precise repositioning of the output range by the user.
The AD8302 comprises a closely matched pair of demodulating In controller applications, the connection between the gain
logarithmic amplifiers, each having a 60 dB measurement range. output pin VMAG and the setpoint control pin MSET is broken.
By taking the difference of their outputs, a measurement of The desired setpoint is presented to MSET and the VMAG
the magnitude ratio or gain between the two input signals is control signal drives an appropriate external variable gain device.
available. These signals may even be at different frequencies, Likewise, the feedback path between the phase output pin VPHS
allowing the measurement of conversion gain or loss. The AD8302 and its setpoint control pin PSET may be broken to allow
may be used to determine absolute signal level by applying the operation as a phase controller.
unknown signal to one input and a calibrated ac reference signal The AD8302 is fabricated on Analog Devices’ proprietary, high
to the other. With the output stage feedback connection dis- performance 25 GHz SOI complementary bipolar IC process. It is
abled, a comparator may be realized, using the setpoint pins available in a 14-lead TSSOP package and operates over a –40°C
MSET and PSET to program the thresholds. to +85°C temperature range. An evaluation board is available.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
may result from its use. No license is granted by implication or otherwise Tel: 781/329–4700 www.analog.com
under any patent or patent rights of Analog Devices. Fax: 781/326-8703 © Analog Devices, Inc., 2002
AD8302–SPECIFICATIONS (TA = 25ⴗC, VS = 5 V, VMAG shorted to MSET, VPHS shorted to PSET, 52.3 ⍀ shunt
resistors connected to INPA and INPB, for Phase measurement PINPA = PINPB, unless otherwise noted.)
Parameter Conditions Min Typ Max Unit
OVERALL FUNCTION
Input Frequency Range >0 2700 MHz
Gain Measurement Range PIN at INPA, PIN at INPB = –30 dBm ± 30 dB
Phase Measurement Range φIN at INPA > φIN at INPB ± 90 Degree
Reference Voltage Output Pin VREF, –40°C ≤ TA ≤ +85°C 1.72 1.8 1.88 V
INPUT INTERFACE Pins INPA and INPB
Input Simplified Equivalent Circuit To AC Ground, f ≤ 500 MHz 3储2 kΩ储pF
Input Voltage Range AC-Coupled (0 dBV = 1 V rms) –73 –13 dBV
re: 50 Ω –60 0 dBm
Center of Input Dynamic Range –43 dBV
–30 dBm
MAGNITUDE OUTPUT Pin VMAG
Output Voltage Minimum 20 × Log (VINPA/VINPB) = –30 dB 30 mV
Output Voltage Maximum 20 × Log (VINPA/VINPB) = +30 dB 1.8 V
Center Point of Output (MCP) VINPA = VINPB 900 mV
Output Current Source/Sink 8 mA
Small Signal Envelope Bandwidth Pin MFLT Open 30 MHz
Slew Rate 40 dB Change, Load 20 pF储10 kΩ 25 V/µs
Response Time
Rise Time Any 20 dB Change, 10%–90% 50 ns
Fall Time Any 20 dB Change, 90%–10% 60 ns
Settling Time Full-Scale 60 dB Change, to 1% Settling 300 ns
PHASE OUTPUT Pin VPHS
Output Voltage Minimum Phase Difference 180 Degrees 30 mV
Output Voltage Maximum Phase Difference 0 Degrees 1.8 V
Phase Center Point When φINPA = φINPB ± 90° 900 mV
Output Current Drive Source/Sink 8 mA
Slew Rate 25 V/µs
Small Signal Envelope Bandwidth 30 MHz
Response Time Any 15 Degree Change, 10%–90% 40 ns
120 Degree Change CFILT = 1 pF, to 1% Settling 500 ns
100 MHz MAGNITUDE OUTPUT
Dynamic Range ± 1 dB Linearity PREF = –30 dBm (VREF = –43 dBV) 58 dB
± 0.5 dB Linearity PREF = –30 dBm (VREF = –43 dBV) 55 dB
Slope From Linear Regression 29 mV/dB
Deviation vs. Temperature Deviation from Output at 25°C
–40°C ≤ TA ≤ +85°C, PINPA = PINPB = –30 dBm 0.25 dB
Deviation from Best Fit Curve at 25°C
–40°C ≤ TA ≤ +85°C, PINPA = ± 25 dB, PINPB = –30 dBm 0.25 dB
Gain Measurement Balance PINPA = PINPB = –5 dBm to –50 dBm 0.2 dB
PHASE OUTPUT
Dynamic Range Less than ± 1 Degree Deviation from Best Fit Line 145 Degree
Less than 10% Deviation in Instantaneous Slope 143 Degree
Slope (Absolute Value) From Linear Regression about –90° or +90° 10 mV/Degree
–40°C ≤ TA ≤ +85°C, Delta Phase = 90 Degrees 0.7 Degree
–40°C ≤ TA ≤ +85°C, Delta Phase = ± 30 Degrees 0.7 Degree
–2– REV. A
AD8302
Parameter Conditions Min Typ Max Unit
Slope From Linear Regression 28.7 mV/dB
PHASE OUTPUT
Slope (Absolute Value) From Linear Regression about –90° or +90° 10.1 mV/Degree
Deviation Linear Deviation from Best Fit Curve at 25°C
Phase Measurement Balance Phase @ INPA = Phase @ INPB, PIN = –5 dBm to –50 dBm 0.8 Degree
–40°C ≤ TA ≤ +85°C, PINPA = ±25 dB, PINPB = –30 dBm 0.33 dB
PHASE OUTPUT
Slope (Absolute Value) From Linear Regression about –90° or +90° 10.2 mV/Degree
Phase Measurement Balance Phase @ INPA = Phase @ INPB, PIN = –5 dBm to –50 dBm 1 Degree
PHASE OUTPUT
Slope (Absolute Value) From Linear Regression about –90° or +90° 10 mV/Degree
REFERENCE VOLTAGE Pin VREF
Output Voltage Load = 2 kΩ 1.7 1.8 1.9 V
PSRR VS = 2.7 V to 5.5 V 0.25 mV/V
Output Current Source/Sink (Less than 1% Change) 5 mA
POWER SUPPLY Pin VPOS
Supply 2.7 5.0 5.5 V
Operating Current (Quiescent) VS = 5 V 19 25 mA
–40°C ≤ TA ≤ +85°C 21 27 mA
Specifications subject to change without notice.
REV. A –3–
AD8302
ABSOLUTE MAXIMUM RATINGS 1 PIN CONFIGURATION
Supply Voltage VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
PSET, MSET Voltage . . . . . . . . . . . . . . . . . . . . . . VS + 0.3 V
COMM 1 14 MFLT
INPA, INPB Maximum Input . . . . . . . . . . . . . . . . . . –3 dBV
Equivalent Power Re. 50 Ω . . . . . . . . . . . . . . . . . . 10 dBm INPA 2 13 VMAG
θJA2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C/W OFSA 3 AD8302 12 MSET
VPOS 4 TOP VIEW 11 VREF

Maximum Junction Temperature . . . . . . . . . . . . . . . . 125°C (Not to Scale)
Operating Temperature Range . . . . . . . . . . . –40°C to +85°C OFSB 5 10 PSET
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C INPB 6 9 VPHS

Lead Temperature Range (Soldering 60 sec) . . . . . . . . 300°C COMM 7 8 PFLT
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
JEDEC 1S Standard (2-layer) board data.
PIN FUNCTION DESCRIPTIONS
Equivalent
Pin No. Mnemonic Function Circuit
1, 7 COMM Device Common. Connect to low impedance ground.
2 INPA High Input Impedance to Channel A. Must be ac-coupled. Circuit A
3 OFSA A capacitor to ground at this pin sets the offset compensation filter corner Circuit A
and provides input decoupling.
4 VPOS Voltage Supply (VS), 2.7 V to 5.5 V
5 OFSB A capacitor to ground at this pin sets the offset compensation filter corner Circuit A
and provides input decoupling.
6 INPB Input to Channel B. Same structure as INPA. Circuit A
8 PFLT Low Pass Filter Terminal for the Phase Output Circuit E
9 VPHS Single-Ended Output Proportional to the Phase Difference between INPA Circuit B
and INPB.
10 PSET Feedback Pin for Scaling of VPHS Output Voltage in Measurement Mode. Circuit D
Apply a setpoint voltage for controller mode.
11 VREF Internally Generated Reference Voltage (1.8 V Nominal) Circuit C
12 MSET Feedback Pin for Scaling of VMAG Output Voltage Measurement Mode. Circuit D
Accepts a set point voltage in controller mode.
13 VMAG Single-Ended Output. Output voltage proportional to the decibel ratio
of signals applied to INPA and INPB. Circuit B
14 MFLT Low Pass Filter Terminal for the Magnitude Output Circuit E
ORDERING GUIDE
Package
Model Temperature Range Package Description Option
AD8302ARU –40°C to +85°C Tube, 14-Lead TSSOP RU-14
AD8302ARU-REEL 13" Tape and Reel
AD8302ARU-REEL7 7" Tape and Reel
AD8302-EVAL Evaluation Board
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although WARNING!
the AD8302 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
ESD SENSITIVE DEVICE
recommended to avoid performance degradation or loss of functionality.
–4– REV. A
AD8302
VPOS
VPOS
100mV
4k⍀
INPA(INPB)
4k⍀ + 750⍀ 25⍀

VMAG
ON TO
(VPHS)
OFSA(OFSB) LOG-AMP
– CLASS A-B
10pF 2k⍀ CONTROL
COMM COMM
Circuit A Circuit B
VPOS VPOS
VPOS
MFLT
VREF 10k⍀ (PFLT)
MSET
10k⍀ (PSET)
1.5pF
10k⍀
5k⍀ ACTIVE LOADS
COMM COMM COMM
Circuit C Circuit D Circuit E

Figure 1. Equivalent Circuits
REV. A –5–
AD8302–Typical Performance Characteristics
(VS = 5 V, VINPB is the reference input and VINPA is swept, unless otherwise noted. All references to dBm are referred to 50 ⍀. For the phase output
curves, the input signal levels are equal, unless otherwise noted.)
2.0 1.80 3.0
900
1.65 2.5
1.8
100 1.50 2.0
1.6
1.35 1.5
ERROR IN VMAG – dB
1.4
1.20 1.0
2200
1.2 1.05 –40ⴗC
VMAG – V
0.5
VMAG – V
1900 +25ⴗC
2700 0.90
1.0 0.0
0.8 0.75 +85ⴗC –0.5

0.60 –1.0
0.6
0.45 –1.5
0.4
0.30 –2.0
0.2 0.15 –2.5
0 0 –3.0
–30 –25 –20 –15 –10 –5 0 5 10 15 20 25 30 –30 –20 –10 0 10 20 30
MAGNITUDE RATIO – dB MAGNITUDE RATIO – dB
TPC 1. Magnitude Output (VMAG) vs. Input Level Ratio TPC 4. VMAG and Log Conformance vs. Input Level Ratio
(Gain) VINPA/VINPB, Frequencies 100 MHz, 900 MHz, (Gain), Frequency 900 MHz, –40 ⴗC, +25 ⴗC, and +85ⴗ C,
1900 MHz, 2200 MHz, 2700 MHz, 25 ⴗC, PINPB = –30 dBm, Reference Level = –30 dBm
(Re: 50 Ω)
2.0 1.80 3.0

1900
1.65 2.5
1.8
1.50 2.0
1.6
1.35 1.5
1.4
2700 1.20 1.0
1.2 1.05
VMAG – V
0.5
VMAG – V
–40ⴗC
1.0 0.90 0.0
+25ⴗC
0.8 0.75 –0.5
+85ⴗC
0.60 –1.0
0.6
2200 0.45 –1.5
0.4
0.30 –2.0
0.2 0.15 –2.5
900
100
0 0 –3.0
–30 –25 –20 –15 –10 –5 0 5 10 15 20 25 30 –30 –20 –10 0 10 20 30
TPC 2. VMAG vs. Input Level Ratio (Gain) VINPA/VINPB, TPC 5. VMAG and Log Conformance vs. Input Level Ratio
Frequencies 100 MHz, 900 MHz, 1900 MHz, 2200 MHz, (Gain), Frequency 1900 MHz, –40 ⴗC, +25 ⴗC, and +85 ⴗC,
2700 MHz, PINPA = –30 dBm Reference Level = –30 dBm
1.80 3.0 1.80 3.0

1.65 2.5 1.65 2.5
1.50 2.0 1.50 2.0
1.35 1.5 1.35 1.5
1.20 1.0 1.20 1.0

–40ⴗC
1.05 1.05 0.5
VMAG – V
0.5
VMAG – V
–40ⴗC
+25ⴗC
0.90 0.0 0.90 0.0
+25ⴗC
0.75 +85ⴗC –0.5
–0.5 0.75
+85ⴗC
0.60 –1.0 0.60 –1.0
0.45 –1.5 0.45 –1.5
0.30 –2.0 0.30 –2.0
0.15 –2.5 0.15 –2.5
0 –3.0 0 –3.0
–30 –20 –10 0 10 20 30 –30 –20 –10 0 10 20 30
TPC 3. VMAG Output and Log Conformance vs. Input TPC 6. VMAG Output and Log Conformance vs. Input
Level Ratio (Gain), Frequency 100 MHz, –40 ⴗC, +25 ⴗC, Level Ratio (Gain), Frequency 2200 MHz, –40 ⴗC, +25 ⴗC,
and +85 ⴗC, Reference Level = –30 dBm and +85 ⴗC, Reference Level = –30 dBm
–6– REV. A
AD8302
3.0 2.0
2.5 1.8
2.0
1.6
1.5 –40 C
+85 C 1.4
1.0
0.5 1.2
VMAG – V
0.0 1.0
–0.5 0.8
–1.0
+85 C 0.6
–1.5 +25 C
–40 C 0.4
–2.0
0.2
–2.5
–3.0 0.0
–30 –25 –20 –15 –10 –5 0 5 10 15 20 25 30 –30 –25 –20 –15 –10 –5 0 5 10 15 20 25 30
TPC 7. Distribution of Magnitude Error vs. Input Level TPC 10. Distribution of VMAG vs. Input Level Ratio (Gain),
Ratio (Gain), Three Sigma to Either Side of Mean, Three Sigma to Either Side of Mean, Frequency 1900 MHz,
Frequency 900 MHz, –40 ⴗC, +25 ⴗC, and +85 ⴗC, Refer- Temperatures Between –40 ⴗC and +85 ⴗC, Reference Level
ence Level = –30 dBm = –30 dBm
3.0 1.8 3.0

–45dBm
2.5 2.5
1.6
2.0 2.0
1.4 –45dBm –30dBm
1.5 1.5
–40 C
+85 C
1.0 1.2 1.0
0.5 –15dBm 0.5

VMAG – V
1.0
0.0 0.0
0.8
–0.5 –30dBm –0.5
–15dBm
–1.0 0.6 –1.0
–1.5 +25 C –1.5

0.4
–40 C +85 C
–2.0 –2.0
0.2
–2.5 –2.5
–3.0 0.0 –3.0

–30 –25 –20 –15 –10 –5 0 5 10 15 20 25 30 –30 –20 –10 0 10 20 30
TPC 8. Distribution of Error vs. Input Level Ratio (Gain), TPC 11. VMAG Output and Log Conformance vs. Input
Three Sigma to Either Side of Mean, Frequency 1900 MHz, Level Ratio (Gain), Reference Level = –15 dBm, –30 dBm,
–40 ⴗC, +25 ⴗC, and +85 ⴗC, Reference Level = –30 dBm and –45 dBm, Frequency 1900 MHz
3.0 1.10
2.5
1.05 PINPA = PINPB + 5dB
2.0
–40 C
1.5
+85 C 1.00
1.0
0.5
VMAG – V
0.95
0.0 PINPA = PINPB
–0.5 0.90
–1.0
+25 C +85 C 0.85
–1.5
–40 C
–2.0
0.80
PINPA = PINPB – 5dB
–2.5
–3.0 0.75
–30 –25 –20 –15 –10 –5 0 5 10 15 20 25 30 –65 –60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5 0
MAGNITUDE RATIO – dB INPUT LEVEL – dBm
TPC 9. Distribution of Magnitude Error vs. Input Level TPC 12. VMAG Output vs. Input Level for P INPA = PINPB,
Ratio (Gain), Three Sigma to Either Side of Mean, PINPA = PINPB + 5 dB, PINPA = PINPB – 5 dB, Frequency 1900 MHz
Frequency 2200 MHz, Temperatures –40 ⴗC, +25 ⴗC, and
+85 ⴗC, Reference Level = –30 dBm
REV. A –7–
AD8302
1.06
1.04 18
1.02 PINPA = PINPB + 5dB
1.00 15
0.98
0.96
0.94 12
PERCENT
VMAG – V
0.92
0.90 9
PINPA = PINPB
0.88
0.86
0.84 6
0.82
0.80
3
0.78 PINPA = PINPB – 5dB
0.76
0.74 0
0 200 400 600 800 1000 1200 1400 1600 1800 2000 2200 0.80 0.85 0.90 0.95 1.00
FREQUENCY – MHz MCP – V
TPC 13. VMAG Output vs. Frequency, for PINPA = PINPB, PINPA TPC 16. Center Point of Magnitude Output (MCP)
= PINPB + 5 dB, and PINPA = PINPB – 5 dB, PINPB = –30 dBm Distribution Frequencies 900 MHz, 17,000 Units
0.4 18
0.2
0 15
CHANGE IN SLOPE – mV
–0.2
12
–0.4
PERCENT
–0.6
9
–0.8
–1.0
6
–1.2
–1.4 3
–1.6
–1.8 0
–40 –20 0 20 40 60 80 85 27.0 27.5 28.0 28.5 29.0 29.5 30.0
TEMPERATURE – ⴗC VMAG SLOPE – mV/dB
TPC 14. Change in VMAG Slope vs. Temperature, Three TPC 17. VMAG Slope, Frequency 900 MHz, 17,000 Units
Sigma to Either Side of Mean, Frequencies 1900 MHz
25 0.032
20
15
0.030
10
SLOPE OF VMAG – V
5
VMAG – mV
0 0.028
–5
–10
0.026
–15
–20
–25 0.024
0
200
400
600
800
1000
1200
1400
1600
1800
2000
2200
2400
2600
2800
–40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90

TEMPERATURE – ⴗC
FREQUENCY – MHz
TPC 15. Change in Center Point of Magnitude Output TPC 18. VMAG Slope vs. Frequency
(MCP) vs. Temperature, Three Sigma to Either Side of
Mean, Frequencies 1900 MHz
–8– REV. A
AD8302
10000
INPUT –50dBm
1000
VMAG – nV/ Hz
INPUT –30dBm
INPUT –10dBm
20mV PER 100
VERTICAL
DIVISION
25ns
HORIZONTAL
10
1k 10k 100k 1M 10M 100M
FREQUENCY – Hz
TPC 19. Magnitude Output Response to 4 dB Step, for TPC 22. Magnitude Output Noise Spectral
PINPB = –30 dBm, PINPA = –32 dBm to –28 dBm, Frequency Density, PINPA = PINPB = –10 dBm, –30 dBm,
1900 MHz, No Filter Capacitor –50 dBm, No Filter Capacitor
10000
INPUT –50dBm
1000
VMAG – nV/ Hz
INPUT –30dBm
20mV PER
VERTICAL
DIVISION 100
INPUT –10dBm
1.00␮s
HORIZONTAL
10
1k 10k 100k 1M 10M 100M
FREQUENCY – Hz
TPC 20. Magnitude Output Response to 4 dB Step, for TPC 23. Magnitude Output Noise Spectral Density, PINPA = PINPB
PINPB = –30 dBm, PINPA = –32 dBm to –28 dBm, Frequency = –10 dBm, –30 dBm, –50 dBm, with Filter Capacitor, C = 1 nF
1900 MHz, 1 nF Filter Capacitor
0.18
0.16
0.14
VMAG (PEAK-TO-PEAK) – V
0.12
0.10
200mV PER 0.08

VERTICAL 2700
1900
DIVISION 0.06
2200
900
0.04
100ns 100
HORIZONTAL 0.02
0.00
–25 –20 –15 –10 –5 0 5 10 15 20 25
MAGNITUDE RATIO – dB
TPC 21. Magnitude Output Response to 40 dB Step, for TPC 24. VMAG Peak-to-Peak Output Induced by Sweeping
PINPB = –30 dBm, PINPA = –50 dBm to –10 dBm, Supply 5 V, Phase Difference through 360 Degrees vs. Magnitude Ratio,
Frequency 1900 MHz, No Filter Capacitor Frequencies 100 MHz, 900 MHz, 1900 MHz, 2200 MHz, and
2700 MHz
REV. A –9–
AD8302
1.8 1.80 10
100MHz 900MHz 1.62 8

1.6
1.44 6
1.4
1900MHz
1.26 4
1.2
ERROR – Degrees
PHASE OUT – V
PHASE OUT – V
2200MHz
1.08 2
2700MHz
1.0
0.90 0
0.8
0.72 –2
0.6
0.54 –4
0.4 0.36 –6
0.2 0.18 –8
0.0 0.00 –10

–180 –140 –100 –60 –20 20 60 100 140 180 –180 –150 –120 –90 –60 –30 0 30 60 90 120 150 180
PHASE DIFFERENCE – Degrees PHASE DIFFERENCE – Degrees
TPC 25. Phase Output (VPHS) vs. Input Phase Difference, TPC 28. VPHS Output and Nonlinearity vs. Input Phase
Input Levels –30 dBm, Frequencies 100 MHz, 900 MHz, Difference, Input Levels –30 dBm, Frequency 1900 MHz
1900 MHz, 2200 MHz, Supply 5 V, 2700 MHz
1.80 10 1.80 10
1.62 8 1.62 8
1.44 6 1.44 6
1.26 4 1.26 4
ERROR – Degrees
ERROR – Degrees
PHASE OUT – V
PHASE OUT – V
1.08 2 1.08 2
0.90 0 0.90 0
0.72 –2 0.72 –2
0.54 –4 0.54 –4
0.36 –6 0.36 –6
0.18 –8 0.18 –8
0.00 –10 0.00 –10

–180 –150 –120 –90 –60 –30 0 30 60 90 120 150 180 –180 –150 –120 –90 –60 –30 0 30 60 90 120 150 180
TPC 26. VPHS Output and Nonlinearity vs. Input Phase TPC 29. VPHS Output and Nonlinearity vs. Input Phase
Difference, Input Levels –30 dBm, Frequency 100 MHz Difference, Input Levels –30 dBm, Frequency 2200 MHz
1.80 10 10
1.62 8 8
1.44 6 6
1.26 4 4
ERROR – Degrees
ERROR – Degrees
+25ⴗC
PHASE OUT – V
1.08 2 2
0.90 0 0
0.72 –2 –2
+85ⴗC
0.54 –4 –4
–40ⴗC
0.36 –6 –6
0.18 –8 –8
0.00 –10 –10

–180 –150 –120 –90 –60 –30 0 30 60 90 120 150 180 –180 –150 –120 –90 –60 –30 0 30 60 90 120 150 180
TPC 27. VPHS Output and Nonlinearity vs. Input Phase TPC 30. Distribution of VPHS Error vs. Input Phase Differ-
Difference, Input Levels –30 dBm, Frequency 900 MHz ence, Three Sigma to Either Side of Mean, Frequency
900 MHz, –40 ⴗC, +25 ⴗC, and +85 ⴗC, Input Levels –30 dBm
–10– REV. A
AD8302
10 0.15
8 0.10
6 0.05 MEAN +3 SIGMA
CHANGE IN VPHS SLOPE – mV

4 0.00
ERROR – Degrees
+25ⴗC –40ⴗC
2 –0.05
0 –0.10
–2 –0.15 MEAN –3 SIGMA

+85ⴗC
–4 –0.20
–6 –0.25
–8 –0.30
–10 –0.35
–180 –150 –120 –90 –60 –30 0 30 60 90 120 150 180 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90
PHASE DIFFERENCE – Degrees TEMPERATURE – ⴗC
TPC 31. Distribution of VPHS Error vs. Input Phase TPC 34. Change in VPHS Slope vs. Temperature, Three
Difference, Three Sigma to Either Side of Mean, Frequency Sigma to Either Side of Mean, Frequency 1900 MHz
1900 MHz, –40 ⴗC, +25 ⴗC, and +85 ⴗC, Supply 5 V, Input
Levels PINPA = PINPB = –30 dBm
10 10
+3 SIGMA
8 5
6 0
4 –5
+85ⴗC +25ⴗC
ERROR – Degrees
2 –10
PERCENT
0 –3 SIGMA
–15
–2 –20
–4 –25
–40ⴗC
–6 –30
–8 –35
–10 –40
–180 –150 –120 –90 –60 –30 0 30 60 90 120 150 180 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90
PHASE DIFFERENCE – Degrees VPHS – mV/Degree
TPC 32. Distribution of VPHS Error vs. Input Phase Differ- TPC 35. Change in Phase Center Point (PCP) vs.
ence, Three Sigma to Either Side of Mean, Frequency Temperature, Three Sigma to Either Side of Mean,
2200 MHz, –40 ⴗC, +25 ⴗC, and +85 ⴗC, Input Levels –30 dBm Frequency 1900 MHz
1.8 18
1.6
15
1.4
1.2 12
VPHS – V
PERCENT
1.0
9
0.8
0.6 6
0.4
3
0.2
0.0 0
–180 –150 –120 –90 –60 –30 0 30 60 90 120 150 180 0.75 0.80 0.85 0.90 0.95 1.00 1.05
PHASE DIFFERENCE – Degrees PCP – V
TPC 33. Distribution of VPHS vs. Input Phase Differ- TPC 36. Phase Center Point (PCP) Distribution, Frequency
ence, Three Sigma to Either Side of Mean, Frequency 900 MHz, 17,000 Units
900 MHz, Temperature between –40 ⴗC and +85 ⴗC, Input
Levels –30 dBm
REV. A –11–
AD8302
16
14
12
10
PERCENT
100mV PER
VERTICAL
8
DIVISION
2
50ns HORIZONTAL
0
9.5 9.7 9.9 10.1 10.3 10.5 10.7 10.9 11.1
VPHS – mV/Degree
TPC 37. VPHS Slope Distribution, Frequency TPC 40. VPHS Output Response to 40 ⴗ Step with Nominal
900 MHz Phase Shift of 90 ⴗ, Input Levels PINPA = PINPB = –30 dBm,
Frequency 1900 MHz,1 pF Filter Capacitor
10000
INPUT –50dBm
1000
VPHS – nV/ Hz
INPUT –30dBm
10mV PER
VERTICAL
INPUT –10dBm
DIVISION
100
50ns HORIZONTAL
10
1k 10k 100k 1M 10M 100M
FREQUENCY – Hz
TPC 38. VPHS Output Response to 4 ⴗ Step with Nominal TPC 41. VPHS Output Noise Spectral Density vs. Frequency,
Phase Shift of 90ⴗ, Input Levels –30 dBm, Frequency PINPA = –30 dBm, PINPB = –10 dBm, –30 dBm, –50 dBm, and
1900 MHz, 25ⴗC, 1 pF Filter Capacitor 90ⴗ Input Phase Difference
1.80
PINPA = –30dBm
1.62
1.44
PINPA = –15dBm
1.26
PHASE OUT – V
1.08
10mV PER PINPA = –45dBm
VERTICAL 0.90
DIVISION
0.72
0.54
0.36
2␮s HORIZONTAL 0.18
0.00
–180 –150 –120 –90 –60 –30 0 30 60 90 120 150 180
PHASE DIFFERENCE – Degrees
TPC 39. VPHS Output Response to 4 ⴗ Step with Nominal TPC 42. Phase Output vs. Input Phase Difference, PINPA =
Phase Shift of 90ⴗ, Input Levels PINPA = PINPB = –30 dBm, PINPB, PINPA = PINPB + 15 dB, PINPA = PINPB – 15 dB, Frequency
Supply 5 V, Frequency 1900 MHz, 25ⴗC, with 100 pF Filter 900 MHz
Capacitor
–12– REV. A
AD8302
12 1.80
PINPA = –15dBm PINPA = –30dBm PINPA = –20dBm
1.62
10
1.44
INSTANTANEOUS SLOPE – mV
ABSOLUTE VALUE OF VPHS
PINPA = –45dBm 1.26

8 PINPA = –40dBm
PHASE OUT – V
1.08
6 0.90
0.72
4
0.54
0.36
2
0.18
PINPA = –30dBm
0 0.00
–180 –150 –120 –90 –60 –30 0 30 60 90 120 150 180 –180 –150 –120 –90 –60 –30 0 30 60 90 120 150 180
TPC 43. Phase Output Instantaneous Slope, TPC 46. Phase Output vs. Input Phase Difference,
PINPA = PINPB, PINPA = PINPB + 15 dB, PINPA = PINPB – 15 dB, PINPA = PINPB, PINPA = PINPB + 10 dB, PINPA = PINPB – 10 dB,
Frequency 900 MHz Frequency 2200 MHz
1.80 12
PINPA = –20dBm PINPA = –20dBm
1.62
10
1.44
ABSOLUTE VALUE OF VPHS PINPA = –30dBm PINPA = –40dBm
1.26
PINPA = –40dBm 8
PHASE OUT – V
1.08
0.90 6
0.72
PINPA = –30dBm 4
0.54
0.36
2
0.18
0.00 0
–180 –150 –120 –90 –60 –30 0 30 60 90 120 150 180 –180 –150 –120 –90 –60 –30 0 30 60 90 120 150 180
TPC 44. Phase Output vs. Input Phase Difference, TPC 47. Phase Output Instantaneous Slope, PINPA = PINPB,
PINPA = PINPB, PINPA = PINPB + 10 dB, PINPA = PINPB – 10 dB, PINPA = PINPB + 10 dB, PINPA = PINPB – 10 dB, Frequency
Frequency 1900 MHz, Supply 5 V 2200 MHz
12 4000 4.0
3500 3.5
10
ABSOLUTE VALUE OF VPHS
3000 REAL SHUNT Z (⍀) 3.0

PINPA = –30dBm
CAPACITANCE – pF
8
RESISTANCE – ⍀
2500 2.5
PINPA = –40dBm
6 2000 2.0
SHUNT R
1500 1.5
4 SHUNT C
1000 1.0
CAPACITANCE SHUNT Z (pF)
2
500 0.5
PINPA = –20dBm
0 0 0.0
–180 –150 –120 –90 –60 –30 0 30 60 90 120 150 180 0 500 1000 1500 2000 2500
PHASE DIFFERENCE – Degrees FREQUENCY – MHz
TPC 45. Phase Output Instantaneous Slope, PINPA = TPC 48. Input Impedance, Modeled as Shunt R in Parallel
PINPB, PINPA = PINPB + 10 dB, PINPA = PINPB – 10 dB, with Shunt C
Frequency 1900 MHz, Supply 5 V
REV. A –13–
AD8302
8 18
6
15
4
12
VREF – mV
PERCENT
2
9
0
6
–2
3
–4
–6 0
–40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 1.74 1.76 1.78 1.80 1.82 1.84 1.86 1.88
TEMPERATURE – ⴗC VREF – V
TPC 49. Change in VREF vs. Temperature, Three Sigma to TPC 51. VREF Distribution, 17,000 Units
Either Side of Mean
120
100
80
NOISE – nV/ Hz
60
40
20
0
1k 10k 100k 1M 10M 100M
FREQUENCY – Hz
TPC 50. VREF Output Noise Spectral Density vs.

Frequency
–14– REV. A
AD8302
GENERAL DESCRIPTION AND THEORY
The AD8302 measures the magnitude ratio, defined here as [
VPHS = VΦ Φ (VINA) − Φ (VINB ) ] (3)
gain, and phase difference between two signals. A pair of where VΦ is the phase slope in mV/degree and Φ is each signal’s
matched logarithmic amplifiers provide the measurement, and relative phase in degrees.
their hard-limited outputs drive the phase detector.
Structure
Basic Theory The general form of the AD8302 is shown in Figure 2. The
Logarithmic amplifiers (log amps) provide a logarithmic com- major blocks consist of two demodulating log amps, a phase
pression function that converts a large range of input signal detector, output amplifiers, a biasing cell, and an output refer-
levels to a compact decibel-scaled output. The general math- ence voltage buffer. The log amps and phase detector process
ematical form is: the high frequency signals and deliver the gain and phase infor-
mation in current form to the output amplifiers. The output
VOUT = VSLP log (VIN / VZ ) (1) amplifiers determine the final gain and phase scaling. External
where VIN is the input voltage, VZ is called the intercept (voltage), filter capacitors set the averaging time constants for the respec-
and VSLP is called the slope (voltage). It is assumed throughout tive outputs. The reference buffer provides a 1.80 V reference
that log(x) represents the log10(x) function. VSLP is thus the voltage that tracks the internal scaling constants.
volts/decade, and since a decade of voltage corresponds to
MFLT
20 dB, V SLP /20 is the volts/dB. V Z is the value of input VIDEO OUTPUT – A + +
VMAG
signal that results in an output of zero and need not correspond INPA 60dB LOG AMPS
– –
to a physically realizable part of the log amp signal range. OFSA (7 DETECTORS)
While the slope is fundamentally a characteristic of the log amp,
the intercept is a function of the input waveform as well.1 MSET
Furthermore, the intercept is typically more sensitive to tem-
PHASE
perature and frequency than the slope. When single log amps COMM
DETECTOR
are used for power measurement, this variability introduces PSET
errors into the absolute accuracy of the measurement since the
intercept represents a reference level.
OFSB 60dB LOG AMPS –
The AD8302 takes the difference in the output of two identical INPB (7 DETECTORS) VPHS
+
log amps, each driven by signals of similar waveforms but at
VIDEO OUTPUT – B PFLT
different levels. Since subtraction in the logarithmic domain
corresponds to a ratio in the linear domain, the resulting VPOS BIAS x3
1.8V
VREF
output becomes:
Figure 2. General Structure
VMAG = VSLP log (VINA / VINB ) (2)
Each log amp consists of a cascade of six 10 dB gain stages with
where VINA and VINB are the input voltages, VMAG is the output seven associated detectors. The individual gain stages have 3 dB
corresponding to the magnitude of the signal level difference, bandwidths in excess of 5 GHz. The signal path is fully differen-
and VSLP is the slope. Note that the intercept, VZ, has dropped tial to minimize the effect of common-mode signals and noise.
out. Unlike the measurement of power, when measuring a dimen- Since there is a total of 60 dB of cascaded gain, slight dc offsets
sionless quantity such as relative signal level, no independent can cause limiting of the latter stages, which may cause mea-
reference or intercept need be invoked. In essence, one signal surement errors for small signals. This is corrected by a feedback
serves as the intercept for the other. Variations in intercept due loop. The nominal high-pass corner frequency, fHP, of this loop
to frequency, process, temperature, and supply voltage affect both is set internally at 200 MHz but can be lowered by adding external
channels identically and hence do not affect the difference. This capacitance to the OFSA and OFSB pins. Signals at frequencies
technique depends on the two log amps being well matched well below the high-pass corner are indistinguishable from dc
in slope and intercept to ensure cancellation. This is the case offsets and are also nulled. The difference in the log amp out-
for an integrated pair of log amps. Note that if the two signals puts is performed in the current domain, yielding by analogy to
have different waveforms (e.g., different peak-to-average ratios) Equation 2:
or different frequencies, an intercept difference may appear, intro- ILA = ISLP log(VINA / VINB ) (4)
ducing a systematic offset.
The log amp structure consists of a cascade of linear/limiting where ILA and ISLP are the output current difference and the
gain stages with demodulating detectors. Further details about characteristic slope (current) of the log amps, respectively. The
the structure and function of log amps can be found in data slope is derived from an accurate reference designed to be insen-
sitive to temperature and supply voltage.
sheets for other log amps produced by Analog Devices.2 The
output of the final stage of a log amp is a fully limited signal The phase detector uses a fully symmetric structure with respect
over most of the input dynamic range. The limited outputs from to its two inputs to maintain balanced delays along both signal
both log amps drive an exclusive-OR style digital phase detector. paths. Fully differential signaling again minimizes the sensitivity
Operating strictly on the relative zero-crossings of the limited sig- to common-mode perturbations. The current-mode equivalent
nals, the extracted phase difference is independent of the original to Equation 3 is:
input signal levels. The phase output has the general form:
[
IPD = IΦ Φ (VINA) − Φ (VINB ) − 90° ] (5)
NOTES
1
See the data sheet for the AD640 for a description of the effect of waveform on where IPD and IΦ are the output current and characteristic slope
the intercept of log amps. associated with the phase detector, respectively. The slope is
2
For example, see the data sheet for the AD8307. derived from the same reference as the log amp slope.
REV. A –15–
AD8302
Note that by convention, the phase difference is taken in the range VP
from –180° to +180°. Since this style of phase detector does not C7
distinguish between ±90°, it is considered to have an unambiguous R4

AD8302
1 COMM MFLT 14
180° phase difference range that can be either 0° to +180° centered C1 VMAG C2
at +90° or 0° to –180° centered at –90°. VINA 2 INPA VMAG 13
R1
The basic structure of both output interfaces is shown in Figure 3. It 3 OFSA MSET 12
accepts a setpoint input and includes an internal integrating/averag- C4
4 VPOS VREF 11
ing capacitor and a buffer amplifier with gain K. External access to C6
these setpoints provides for several modes of operation and enables 5 OFSB PSET 10
R2
flexible tailoring of the gain and phase transfer characteristics. The VINB 6 INPB VPHS 9 VPHS
setpoint interface block, characterized by a transresistance RF, gener- C5
ates a current proportional to the voltage presented to its input pin, C3
7 COMM PFLT 8
C8
MSET or PSET. A precise offset voltage of 900 mV is introduced
internally to establish the center-point (VCP) for the gain and phase Figure 4. Basic Connections in Measurement Mode with
functions, i.e., the setpoint voltage that corresponds to a gain of 0 dB
30 mV/dB and 10 mV/Degree Scaling
and a phase difference of 90°. This setpoint current is subtracted
from the signal current, IIN, coming from the log amps in the gain In the low frequency limit, the gain and phase transfer functions
channel or from the phase detector in the phase channel. The result- given in Equations 4 and 5 become:
ing difference is integrated on the averaging capacitors at either pin
MFLT or PFLT and then buffered by the output amplifier to the VMAG = RF ISLP log(VINA / VINB ) + VCP or (8a)
VMAG = (RF ISLP / 20) (PINA − PINB ) + VCP

respective output pins, VMAG and VPHS. With this open-loop
arrangement, the output voltage is a simple integration of the differ- (8b)
ence between the measured gain/phase and the desired setpoint:
(
VPHS = –RF IΦ |Φ (VINA) − Φ (VINB ) |–90° + VCP ) (9)
VOUT = RF (IIN − IFB ) / (sT ) (6) which are illustrated in Figure 5. In Equation 8b, PINA and PINB are
where IFB is the feedback current equal to (VSET – VCP)/RF, VSET the power in dBm equivalent to VINA and VINB at a specified refer-
is the setpoint input, and T is the integration time constant equal ence impedance. For the gain function, the slope represented by
to RFCAVE/K, where CAVE is the parallel combination of the inter- RF ISLP is 600 mV/decade or, dividing by 20 dB/decade, 30 mV/dB.
With a center point of 900 mV for 0 dB gain, a range of –30 dB to
nal 1.5 pF and the external capacitor CFLT.
+30 dB covers the full-scale swing from 0 V to 1.8 V. For the phase
function, the slope represented by RFIΦ is 10 mV/degree. With a
1.5pF
center point of 900 mV for 90°, a range of 0° to 180° covers the
MFLT/PFLT
+ CFLT
full-scale swing from 1.8 V to 0 V. The range of 0° to –180° covers
IIN = ILA OR IPD K VMAG/VPHS the same full-scale swing but with the opposite slope.
–
VCP = 900mV 1.8V
IFB
+
RF MSET/PSET
+
20k⍀ 30mV/dB
VMAG
Figure 3. Simplified Block Diagram of the Output Interface 900mV VCP
BASIC CONNECTIONS
Measurement Mode
The basic function of the AD8302 is the direct measurement of gain
and phase. When the output pins, VMAG and VPHS, are connected 0V
directly to the feedback setpoint input pins, MSET and PSET, the –30 0 +30
default slopes and center points are invoked. This basic connection MAGNITUDE RATIO – dB
shown in Figure 4 is termed the measurement mode. The current 1.8V
from the setpoint interface is forced by the integrator to be equal to
the signal currents coming from the log amps and phase detector.
The closed loop transfer function is thus given by: +10mV/DEG –10mV/DEG
VOUT = ( I IN RF + VCP ) / (1 + sT )
VPHS
(7)
900mV VCP
The time constant T represents the single-pole response to the enve-
lope of the dB-scaled gain and the degree-scaled phase functions. A
small internal capacitor sets the maximum envelope bandwidth to
approximately 30 MHz. If no external CFLT is used, the AD8302
can follow the gain and phase envelopes within this bandwidth. If 0V
longer averaging is desired, CFLT can be added as necessary accord- –180 –90 0 90 180
ing to T (ns) = 3.3 × CAVE (pF). For best transient response with PHASE DIFFERENCE – Degrees
minimal overshoot, it is recommended that 1 pF minimum value Figure 5. Idealized Transfer Characteristics for the Gain
external capacitors be added to the MFLT and PFLT pins. and Phase Measurement Mode
–16– REV. A
AD8302
Interfacing to the Input Channels Dynamic Range
The single-ended input interfaces for both channels are identical. The maximum measurement range for the gain subsystem is lim-
Each consists of a driving pin, INPA and INPB, and an ac- ited to a total of 60 dB distributed from –30 dB to +30 dB. This
grounding pin, OFSA and OFSB. All four pins are internally means that both gain and attenuation can be measured. The limits
dc-biased at about 100 mV from the positive supply and should are determined by the minimum and maximum levels that each
be externally ac-coupled to the input signals and to ground. For individual log amp can detect. In the AD8302, each log amp can
the signal pins, the coupling capacitor should offer negligible detect inputs ranging from –73 dBV [(223 µV, –60 dBm re: 50 Ω
impedance at the signal frequency. For the grounding pins, the to –13 dBV (223 mV, 0 dBm re: 50 Ω)]. Note that log
coupling capacitor has two functions: It provides ac grounding amps respond to voltages and not power. An equivalent power
and sets the high-pass corner frequency for the internal offset can be inferred given an impedance level, e.g., to convert from
compensation loop. There is an internal 10 pF capacitor to ground dBV to dBm in a 50 Ω system, simply add 13 dB. To cover
that sets the maximum corner to approximately 200 MHz. the entire range, it is necessary to apply a reference level to one log
The corner can be lowered according the formula f HP (MHz) = amp that corresponds precisely to its midrange. In the AD8302,
2/CC(nF), where CC is the total capacitance from OFSA or OFSB this level is at –43 dBV, which corresponds to –30 dBm in a 50 Ω
to ground, including the internal 10 pF. environment. The other channel can now sweep from its low end,
The input impedance to INPA and INPB is a function of 30 dB below midrange, to its high end, 30 dB above midrange. If
frequency, the offset compensation capacitor, and package the reference is displaced from midrange, some measurement
parasitics. At moderate frequencies above fHP, the input network range will be lost at the extremes. This can occur either if the log
can be approximated by a shunt 3 kΩ resistor in parallel with a amps run out of range or if the rails at ground or 1.8 V are reached.
2 pF capacitor. At higher frequencies, the shunt resistance Figure 7 illustrates the effect of the reference channel level placement.
decreases to approximately 500 Ω. The Smith Chart in Figure 6 If the reference is chosen lower than midrange by 10 dB, then the
shows the input impedance over the frequency range 100 MHz lower limit will be at –20 dB rather than –30 dB. If the reference chosen
to 3 GHz. is higher by 10 dB, the upper limit will be 20 dB rather than 30 dB.
MAX RANGE FOR VREF = VREFOPT
1.80
VMAG – V
100MHz
0.90
VREF < VREFOPT VREF > VREFOPT
900MHz
1.8GHz
2.2GHz
2.7GHz
3.0GHz
–30 0 +30
GAIN MEASUREMENT RANGE – dB
Figure 6. Smith Chart Showing the Input Impedance of a
Single Channel from 100 MHz to 3 GHz Figure 7. The Effect of Offsetting the Reference Level Is to
Reduce the Maximum Dynamic Range
A broadband resistive termination on the signal side of the coupling
capacitors can be used to match to a given source impedance. The phase measurement range is of 0° to 180°. For phase differ-
The value of the termination resistor, RT, is determined by: ences of 0° to –180°, the transfer characteristics are mirrored as
shown in Figure 5, with a slope of the opposite sign. The phase
RT = RIN RS / (RIN − RS ) (10) detector responds to the relative position of the zero crossings
between the two input channels. At higher frequencies, the finite
where RIN is the input resistance and RS the source impedance.
rise and fall times of the amplitude limited inputs create an
At higher frequencies, a reactive, narrow-band match might be
ambiguous situation that leads to inaccessible dead zones at the
desirable to tune out the reactive portion of the input impedance.
0° and 180° limits. For maximum phase difference coverage, the
An important attribute of the two-log-amp architecture is that if
reference phase difference should be set to 90°.
both channels are at the same frequency and have the same input
network, then impedance mismatches and reflection losses become
essentially common-mode and hence do not impact the relative
gain and phase measurement. However, mismatches in these
external components can result in measurement errors.
REV. A –17–
AD8302
Cross Modulation of Magnitude and Phase reference that determines the nominal center point, their
At high frequencies, unintentional cross coupling between signals tracking with temperature, supply, and part-to-part variations
in Channels A and B inevitably occurs due to on-chip and board- should be better in comparison to a fixed external voltage. If the
level parasitics. When the two signals presented to the AD8302 center point is shifted to 0 dB in the previous example where
inputs are at very different levels, the cross coupling introduces the slope was doubled, then the range spans from –15 dB at
cross modulation of the phase and magnitude responses. If the two VMAG = 0 V to 15 dB at VMAG = 1.8 V.
signals are held at the same relative levels and the phase between
them is modulated then only the phase output should respond.
R1
Due to phase-to-amplitude cross modulation, the magnitude out- NEW SLOPE = 30mV/dB ⴛ 1ⴙ
10k⍀
put shows a residual response. A similar effect occurs when the VMAG
relative phase is held constant while the magnitude difference is MSET

R1
modulated, i.e., an expected magnitude response and a residual

20k⍀
phase response are observed due to amplitude-to-phase cross 20k⍀
modulation. The point where these effects are noticeable depends VREF
on the signal frequency and the magnitude of the difference. Typi-
cally, for differences <20 dB, the effects of cross modulation are
negligible at 900 MHz. Figure 9. The Center Point Is Repositioned with the Help
of the Internal Reference Voltage of 1.80 V
Modifying the Slope and Center Point
The default slope and center point values can be modified with Comparator and Controller Modes
the addition of external resistors. Since the output interface The AD8302 can also operate in a comparator mode if used in
blocks are generalized for both magnitude and phase functions, the arrangement shown in Figure 10 where the DUT is the element
the scaling modification techniques are equally valid for both to be evaluated. The VMAG and VPHS pins are no longer
outputs. Figure 8 demonstrates how a simple voltage divider connected to MSET and PSET. The trip-point thresholds for the
from the VMAG and VPHS pins to the MSET and PSET pins gain and phase difference comparison are determined by the
can be used to modify the slope. The increase in slope is given by voltages applied to pins MSET and PSET according to:
1 + R1/(R2储20 kΩ). Note that it may be necessary to account for
the MSET and PSET input impedance of 20 kΩ which has a ±20% VMSET (V ) = 30 mV / dB × GainSP (dB ) + 900 mV (11)
( )
manufacturing tolerance. As is generally true in such feedback
systems, envelope bandwidth is decreased and the output noise VPSET (V ) = −10 mV/ ° × | Phase SP ( °)|–90° + 900 mV (12)
transferred from the input is increased by the same factor. For
where GainSP (dB) and PhaseSP (°) are the desired gain and
example, by selecting R1 and R2 to be 10 kΩ and 20 kΩ,
phase thresholds. If the actual gain and phase between the two
respectively, gain slope increases from the nominal 30 mV/dB
input channels differ from these thresholds, the VMAG and VPHS
by a factor of 2 to 60 mV/dB. The range is reduced by a factor
outputs toggle like comparators, i.e.,
of 2 and the new center point is at –15 dB, i.e., the range now
extends from –30 dB, corresponding to VMAG = 0 V, to 0 dB,
1.8 V if Gain > Gain SP
corresponding to VMAG = 1.8 V. VMAG = (13)
0 V if Gain < Gain SP
1.8 V if Phase > PhaseSP

VMAG
NEW SLOPE = 30mV/dB ⴛ 1ⴙ
R1 VPHS = (14)
R1
R2||R20k⍀
0 V if Phase < PhaseSP
MSET
20k⍀ R2
VP
Figure 8. Increasing the Slope Requires the Inclusion of a C7

AD8302
Voltage Divider R4
1 COMM MFLT 14
Repositioning the center point back to its original value of 0 dB C1 C2
VINA 2 INPA VMAG 13 VMAG
simply requires that an appropriate voltage be applied to the R1
grounded side of the lower resistor in the voltage divider. This 3 OFSA MSET 12 VMSET
C4
voltage may be provided externally or derived from the internal 4 VPOS VREF 11
reference voltage on pin VREF. For the specific choice of R2 = C6
5 OFSB PSET 10 VPSET
20 kΩ, the center point is easily readjusted to 0 dB by connecting R2
the VREF pin directly to the lower pin of R2 as shown in Figure 9. VINB 6 INPB VPHS 9 VPHS
C5
The increase in slope is now simplified to 1 + R1/10 kΩ. Since this 7 COMM PFLT 8
1.80 V reference voltage is derived from the same band gap C3 C8
Figure 10. Disconnecting the Feedback to the Setpoint

Controls, the AD8302 Operates in Comparator Mode
–18– REV. A
AD8302
The comparator mode can be turned into a controller mode by When the insertion phase is nominal, the VPHS output is 900 mV.
closing the loop around the VMAG and VPHS outputs. Deviations from the nominal are reported with a 10 mV/degree
Figure 11 illustrates a closed loop controller that stabilizes the gain scaling. Table I gives suggested component values for the
and phase of a DUT with gain and phase adjustment elements. measurement of an amplifier with a nominal gain of 10 dB and
If VMAG and VPHS are properly conditioned to drive gain and an input power of –10 dBm.
phase adjustment blocks preceding the DUT, the actual gain and
phase of the DUT will be forced toward the prescribed setpoint
ATTENA
gain and phase given in Equations 11 and 12. These are essentially
AGC and APC loops. Note that as with all control loops of this kind, DCA
VP
loop dynamics and appropriate interfaces all must be considered
C7
OUTPUT
in more detail.
AD8302
R4
1 COMM MFLT 14 C2
C1
H
2 INPA VMAG 13
INPA VMAG R1 R5
⌬MAG 3 OFSA MSET 12
MAG
MSET C4
SETPOINT 4 VPOS VREF 11
AD8302 “BLACK BOX” C6
PSET PHASE
SETPOINT 5 OFSB PSET 10
INPB VPHS R2 H
6 INPB VPHS 9
⌬⌽
C5 R6
7 COMM PFLT 8
C3 C8
INPUT
Figure 11. By Applying Overall Feedback to a DUT Via DCB
ATTENB
External Gain and Phase Adjusters, the AD8302 Acts
as a Controller
APPLICATIONS Figure 12. Using the AD8302 to Measure the Gain and
Measuring Amplifier Gain and Compression Insertion Phase of an Amplifier or Mixer
The most fundamental application of AD8302 is the monitoring
of the gain and phase response of a functional circuit block such as Table I. Component Values for Measuring a 10 dB Amplifier
an amplifier or a mixer. As illustrated in Figure 12, directional with an Input Power of –10 dBm
couplers, DCB and DCA, sample the input and output signals of
Component Value Quantity
the “Black Box” DUT. The attenuators ensure that the signal
levels presented to the AD8302 fall within its dynamic range. R1, R2 52.3 Ω 2
From the discussion in the Dynamic Range section, the optimal R5, R6 100 Ω 2
choice places both channels at POPT = –30 dBm referenced to 50 Ω, C1, C4, C5, C6 0.001 µF 4
which corresponds to –43 dBV. To achieve this, the combination C2, C8 Open
of coupling factor and attenuation are given by: C3 100 pF 1
C7 0.1 µF 1
CB + LB = PIN − POPT (15) AttenA 10 dB (See Text) 1
C A + L A = PIN + GAIN NOM − POPT (16) AttenB 1 dB (See Text) 1
DCA, DCB 20 dB 2
where CB and CA are the coupling coefficients, LB and LA are the
attenuation factors, and GAINNOM is the nominal DUT gain. If The gain measurement application can also monitor gain and
identical couplers are used for both ports, then the difference in the phase distortion in the form of AM-AM (gain compression) and
two attenuators compensates for the nominal DUT gain. When the AM-PM conversion. In this case, the nominal gain and phase
actual gain is nominal, the VMAG output is 900 mV, corresponding corresponds to those at low input signal levels. As the input level
to 0 dB. Variations from nominal gain appear as a deviation from is increased, output compression and excess phase shifts are
900 mV or 0 dB with a 30 mV/dB scaling. Depending on the nominal measured as deviations from the low level case. Note that the signal
insertion phase associated with DUT, the phase measurement may levels over which the input is swept must remain within the dynamic
require a fixed phase shift in series with one of the channels to bring range of the AD8302 for proper operation.
the nominal phase difference presented to the AD8302 near the
optimal 90° point.
REV. A –19–
AD8302
Reflectometer The measurement accuracy can be compromised if board
The AD8302 can be configured to measure the magnitude ratio level details are not addressed. Minimize the physical distance
and phase difference of signals that are incident on and reflected between the series connected couplers since the extra path
from a load. The vector reflection coefficient, ⌫, is defined as, length adds phase error to ⌫. Keep the paths from the couplers
to the AD8302 as well matched as possible since any differences
Γ = Reflected Voltage / Incident Voltage = ( Z L − ZO ) / ( Z L + ZO ) (17) introduce measurement errors. The finite directivity, D, of the
where ZL is the complex load impedance and ZO is the charac- couplers sets the minimum detectable reflection coefficient, i.e.,
teristic system impedance. | ΓMIN(dB)|<|D(dB)|.
The measured reflection coefficient can be used to calculate the SOURCE
level of impedance mismatch or standing wave ratio (SWR) of a
particular load condition. This proves particularly useful in diag- INCIDENT REFLECTED ZLOAD
WAVE WAVE
nosing varying load impedances such as antennas that can degrade 20dB 1dB
performance and even cause physical damage. The vector
reflectometer arrangement given in Figure 13 consists of a pair
of directional couplers that sample the incident and reflected sig-
nals. The attenuators reposition the two signal levels within the R2 R1
dynamic range of the AD8302. In analogy to Equations 15 and
16, the attenuation factors and coupling coefficients are given by: C5 C6 C4 C1
C3
CB + LB = PIN − POPT (18) R4
VP
C7
C A + LA = PIN + ΓNOM − POPT (19)
where ⌫NOM is the nominal reflection coefficient in dB and is
negative for passive loads. Consider the case where the incident
signal is 10 dBm and the nominal reflection coefficient is –19 dB. AD8302 C2
As shown in Figure 13, using 20 dB couplers on both sides and 1 COMM MFLT 14
–30 dBm for POPT, the attenuators for Channel A and B paths 2 INPA VMAG 13 ⌫
are 1 dB and 20 dB, respectively. The magnitude and phase of R5
3 OFSA MSET 12
the reflection coefficient are available at the VMAG and VPHS
pins scaled to 30 mV/dB and 10 mV/degree. When ⌫ is –19 dB, 4 VPOS VREF 11
the VMAG output is 900 mV. 5 OFSB PSET 10
6 INPB VPHS 9 ⌫
R6
7 COMM PFLT 8
C8
Figure 13. Using the AD8302 to Measure the Vector

Reflection Coefficient Off an Arbitrary Load
–20– REV. A
AD8302
VP
VP
C7
R4 AD8302
1 COMM MFLT 14
C1 C2 GAIN
INPA 2 INPA VMAG 13 R5 Table II. P1 Pin Allocations
R1
3 OFSA MSET 12 SW1 1 Common
C4 R7 GSET 2 VPOS
GND 4 VPOS VREF 11 VREF
C6 SW2 R3 R9 3 Common
5 OFSB PSET 10
R2 R8
INPB 6 INPB VPHS 9 PSET
C5
7 COMM PFLT 8 PHASE
C3 C8 R6
Figure 14. Evaluation Board Schematic
Figure 15a. Component Side Metal of Evaluation Board Figure 15b. Component Side Silkscreen of Evaluation Board
Table III. Evaluation Board Configuration Options
Component Function Default Condition

P1 Power Supply and Ground Connector: Pin 2 VPOS and Pins 1 and 3 Ground. Not Applicable
R1, R2 Input Termination. Provide termination for input sources. R1 = R2 = 52.3 Ω (Size 0402)
R3 VREF Output Load. This load is optional and is meant to allow the user to simulate R3 = 1 kΩ (Size 0603)
their circuit loading of the device.
R5, R6, R9 Snubbing Resistor R5 = R6 = 0 Ω (Size 0603)
R9 = 0 Ω (Size 0603)
C3, C7, R4 Supply Decoupling C3 = 100 pF (Size 0603)
C7 = 0.1 µF (Size 0603)
R4 = 0 Ω (Size 0603)
C1, C5 Input AC-Coupling Capacitors C1 = C5 = 1 nF (Size 0603)
C2, C8 Video Filtering. C2 and C8 limit the video bandwidth of the gain and phase C2 = C8 = Open (Size 0603)
output respectively.
C4, C6 Offset Feedback. These set the high-pass corner of the offset cancellation loop
and thus with the input ac-coupling capacitors the minimum operating frequency. C4 = C6 = 1 nF (Size 0603)
SW1 GSET Signal Source. When SW1 is in the position shown, the device is in gain SW1 = Installed
measure mode; when switched, it operates in comparator mode and a signal
must be applied to GSET.
SW2 PSET Signal Source. When SW2 is in the position shown, the device is in phase SW1 = Installed
measure mode; when switched, it operates in comparator mode and a signal
must be applied to PSET.
REV. A –21–
AD8302
CHARACTERIZATION SETUPS AND METHODS Phase
The general hardware configuration used for most of the AD8302 The majority of the VPHS output data was collected by generating
characterization is shown in Figure 16. The characterization board phase change, again by operating the two input sources with a
is similar to the Customer Evaluation Board. Two reference-locked small frequency offset (normally 100 kHz) using the same
R and S SMT03 signal generators are used as the inputs to configuration shown in Figure 16. Although this method gives
INPA and INPB, while the gain and phase outputs are monitored excellent linear phase change, good for measurement of slope
using both a TDS 744A oscilloscope with 10× high impedance and linearity, it lacks an absolute phase reference point. In the
probes and Agilent 34401A multimeters. curves showing swept phase, the phase at which the VPHS is the
Gain same as VPHS with no input signal is taken to be –90° and all
The basic technique used to evaluate the static gain (VMAG) other angles are references to there. Typical Performance Curves
performance was to set one source to a fixed level and sweep the show two figures of merit; instantaneous slope and error. Instanta-
amplitude of the other source, while measuring the VMAG output neous slope, as shown in TPCs 43, 44, 45, and 47, was calculated
with the DMM. In practice, the two sources were run at 100 kHz simply by taking the delta in VPHS over angular change for adjacent
frequency offset and average output measured with the DMM to measurement points.
alleviate errors that might be induced by gain/phase modulation
TEKTRONIX
due to phase jitter between the two sources. TEKTRONIX TDS 744A
VX1410A OSCILLOSCOPE
The errors stated are the difference between a best fit line calcu-
lated by a linear regression and the actual measured data divided R&S MULTIMETER/
SIGNAL GENERATOR 3dB INPA VMAG OSCILLOSCOPE
by the slope of the line to give an error in V/dB. The referred to SMTO3
25°C error uses this same method while always using the slope EVB
VREF HP 34401A
MULTIMETER
and intercept calculated for that device at 25°C. R&S
SIGNAL GENERATOR 3dB INPB VPHS
Response measurement made of the VMAG output used the SMTO3
configuration shown in Figure 17. The variable attenuator, SAME SETUP AS

VMAG
Alpha AD260, is driven with a HP8112A pulse generator pro-
ducing a change in RF level within 10 ns. Figure 16. Primary Characterization Setup
Noise spectral density measurements were made using a
HP3589A with the inputs delivered through a Narda 4032C TEKTRONIX
VX1410A
90° phase splitter.
To measure the modulation of VMAG due to phase variation FIXED
TEKTRONIX
3dB INPA VMAG P TDS 744A
again the sources were run at a frequency offset, fOS, effectively R&S ATTEN OSCILLOSCOPE
creating a continuous linear change in phase going through 360° SIGNAL VREF
GENERATOR EVB
once every 1/fOS seconds. The VMAG output is then measured SMTO3 VARIABLE VPHS
3dB INPB
with a DSO. When perceivable, only at high frequencies and ATTEN
large input magnitude differences, the linearly ramping phase SPLITTER

creates a near sinusoid output riding on the expected VMAG dc PULSE
GENERATOR
output level. The curves in TPC 24 show the peak-to-peak out-
put level measured with averaging. Figure 17. VMAG Dynamic Performance Measurement Setup
–22– REV. A
AD8302
OUTLINE DIMENSIONS
14-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-14)
Dimensions shown in millimeters
5.10
5.00
4.90
14 8
4.50 6.40
4.40 BSC
4.30
1 7
PIN 1
0.65
1.05 BSC
1.00 1.20
MAX 0.75
0.80 8ⴗ 0.60
0.15
COPLANARITY 0.30 0ⴗ 0.45
0.05 SEATING 0.20
0.19 PLANE 0.09
COMPLIANT TO JEDEC STANDARDS MO-153AB-1
REV. A –23–
Revision History
Location Page
7/02—Data Sheet changed from REV. 0 to REV. A.
TPCs 3 through 6 replaced . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
C02492–0–7/02(A)
PRINTED IN U.S.A.
–24– REV. A
Low Power, 8.5 mW, 2.3 V to 5.5 V,
Programmable Waveform Generator
Data Sheet AD9837
FEATURES GENERAL DESCRIPTION
Digitally programmable frequency and phase The AD9837 is a low power, programmable waveform generator
8.5 mW power consumption at 2.3 V capable of producing sine, triangular, and square wave outputs.
MCLK speed: 16 MHz (B grade), 5 MHz (A grade) Waveform generation is required in various types of sensing,
28-bit resolution: 0.06 Hz at 16 MHz reference clock actuation, and time domain reflectometry (TDR) applications.
Sinusoidal, triangular, and square wave outputs The output frequency and phase are software programmable,
2.3 V to 5.5 V power supply allowing easy tuning. The frequency registers are 28 bits wide:
3-wire SPI interface with a 16 MHz clock rate, resolution of 0.06 Hz can be achieved;
Extended temperature range: −40°C to +125°C with a 5 MHz clock rate, the AD9837 can be tuned to 0.02 Hz
Power-down option resolution.
10-lead LFCSP
The AD9837 is written to via a 3-wire serial interface. This serial
APPLICATIONS interface operates at clock rates up to 40 MHz and is compatible
Frequency stimulus/waveform generation with DSP and microcontroller standards. The device operates
Liquid and gas flow measurement with a power supply from 2.3 V to 5.5 V.
Sensory applications: proximity, motion, The AD9837 has a power-down (sleep) function. Sections of the
and defect detection device that are not being used can be powered down to minimize
Line loss/attenuation the current consumption of the part. For example, the DAC can
Test and medical equipment be powered down when a clock output is being generated.
Sweep/clock generators
The AD9837 is available in a 10-lead LFCSP_WD package.
Time domain reflectometry (TDR) applications
FUNCTIONAL BLOCK DIAGRAM

AGND DGND VDD CAP/2.5V
ON-BOARD
MCLK REGULATOR REFERENCE
AVDD/ FULL-SCALE COMP
DVDD CONTROL
2.5V
28-BIT FREQ0 REG

PHASE 12
SIN MUX 10-BIT DAC
MUX ACCUMULATOR ROM
(28-BIT)
28-BIT FREQ1 REG
MSB
12-BIT PHASE0 REG

12-BIT PHASE1 REG MUX
DIVIDE VOUT
MUX
BY 2
16-BIT CONTROL REGISTER R
200Ω
SERIAL INTERFACE
AND
CONTROL LOGIC AD9837
09070-001
FSYNC SCLK SDATA
Figure 1.
Rev. A Document Feedback

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AD9837 Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1 Functional Description .................................................................. 13
Applications ....................................................................................... 1 Serial Interface ............................................................................ 13
General Description ......................................................................... 1 Latency Period ............................................................................ 13
Functional Block Diagram .............................................................. 1 Control Register ......................................................................... 13
Revision History ............................................................................... 2 Frequency and Phase Registers ................................................ 15
Specifications..................................................................................... 3 Reset Function ............................................................................ 16
Timing Characteristics ................................................................ 4 Sleep Function ............................................................................ 16
Absolute Maximum Ratings............................................................ 5 VOUT Pin ................................................................................... 16
Thermal Resistance ...................................................................... 5 Powering Up the AD9837 ......................................................... 16
ESD Caution .................................................................................. 5 Applications Information .............................................................. 19
Pin Configuration and Function Descriptions ............................. 6 Grounding and Layout .............................................................. 19
Typical Performance Characteristics ............................................. 7 Interfacing to Microprocessors................................................. 19
Test Circuit ........................................................................................ 9 Evaluation Board ............................................................................ 21
Terminology .................................................................................... 10 System Demonstration Platform .............................................. 21
Theory of Operation ...................................................................... 11 AD9837 to SPORT Interface ..................................................... 21
Circuit Description ......................................................................... 12 Evaluation Kit ............................................................................. 21
Numerically Controlled Oscillator Plus Phase Modulator ... 12 Crystal Oscillator vs. External Clock ....................................... 21
SIN ROM ..................................................................................... 12 Power Supply............................................................................... 21
Digital-to-Analog Converter (DAC) ....................................... 12 Evaluation Board Schematics ................................................... 22
Regulator...................................................................................... 12 Evaluation Board Layout ........................................................... 24
Outline Dimensions ....................................................................... 25
Ordering Guide .......................................................................... 25
REVISION HISTORY
12/12—Rev. 0 to Rev. A
Changed Input Current, IINH/IINL from 10 mA to 10 µA.............. 3
Updated Outline Dimensions ....................................................... 25
4/11—Revision 0: Initial Version
Rev. A | Page 2 of 28
Data Sheet AD9837
SPECIFICATIONS
VDD = 2.3 V to 5.5 V, AGND = DGND = 0 V, TA = TMIN to TMAX, unless otherwise noted.
Table 1.
Parameter 1 Min Typ Max Unit Test Conditions/Comments
SIGNAL DAC SPECIFICATIONS
Resolution 10 Bits
Update Rate
A Grade 5 MSPS
B Grade 16 MSPS
VOUT Maximum 0.645 V
VOUT Minimum 37 mV
Vp-p 0.610 V
VOUT TC 200 ppm/°C
DC Accuracy
Integral Nonlinearity (INL) ±1.0 LSB
Differential Nonlinearity (DNL) ±0.5 LSB
DDS SPECIFICATIONS
Dynamic Specifications
Signal-to-Noise Ratio (SNR)
A Grade −64 dB fMCLK = 5 MHz, fOUT = fMCLK/4096
B Grade −64 dB fMCLK = 16 MHz, fOUT = fMCLK/4096
Total Harmonic Distortion (THD)
A Grade −68 dBc fMCLK = 5 MHz, fOUT = fMCLK/4096
B Grade −68 dBc fMCLK = 16 MHz, fOUT = fMCLK/4096
Spurious-Free Dynamic Range (SFDR)
Wideband (0 to Nyquist)
Narrow-Band (±200 kHz)
Clock Feedthrough −67 dBc
Wake-Up Time 1 ms
LOGIC INPUTS
Input High Voltage, VINH 1.7 V 2.3 V to 2.7 V power supply
2.0 V 2.7 V to 3.6 V power supply
Input Low Voltage, VINL 0.5 V 2.3 V to 2.7 V power supply
Input Current, IINH/IINL 10 µA
Input Capacitance, CIN 3 pF
POWER SUPPLIES fMCLK = 16 MHz, fOUT = fMCLK/4096
VDD 2.3 5.5 V
IDD
A Grade 3.7 5.0 mA IDD code dependent; see Figure 6
B Grade 4.5 5.5 mA IDD code dependent; see Figure 7
Low Power Sleep Mode 0.5 0.8 mA DAC powered down (SLEEP1 and
SLEEP12 bits = 11; see Table 15)
1
Operating temperature range is −40°C to +125°C; typical specifications are at 25°C.
AD9837 Data Sheet
TIMING CHARACTERISTICS
VDD = 2.3 V to 5.5 V, AGND = DGND = 0 V, unless otherwise noted.
Table 2.
Parameter 1 Limit at TMIN to TMAX Unit Description
t1 62.5 ns min MCLK period (fMCLK = 16 MHz)
t2 25 ns min MCLK high duration (fMCLK = 16 MHz)
t3 25 ns min MCLK low duration (fMCLK = 16 MHz)
t4 25 ns min SCLK period
t5 10 ns min SCLK high duration
t6 10 ns min SCLK low duration
t7 5 ns min FSYNC to SCLK falling edge setup time
t8 10 ns min SCLK falling edge to FSYNC rising edge time
t4 − 5 ns max
t9 5 ns min Data setup time
t10 3 ns min Data hold time
t11 5 ns min SCLK high to FSYNC falling edge setup time
1
Guaranteed by design; not production tested.
Timing Diagrams
t1
MCLK
09070-003
t2
t3
Figure 2. Master Clock
t11 t5 t4
SCLK
t7 t6 t8
FSYNC
t10
t9
09070-004
SDATA D15 D14 D2 D1 D0 D1 5 D14
Figure 3. Serial Timing
Data Sheet AD9837
ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted. THERMAL RESISTANCE
Table 3. θJA is specified for the worst-case conditions, that is, a device
Parameter Rating soldered in a circuit board for surface-mount packages.
VDD to AGND −0.3 V to +6 V Table 4. Thermal Resistance
VDD to DGND −0.3 V to +6 V Package Type θJA θJC Unit
AGND to DGND −0.3 V to +0.3 V 10-Lead LFCSP_WD (CP-10-9) 206 44 °C/W
CAP/2.5V 2.75 V
Digital I/O Voltage to DGND −0.3 V to VDD + 0.3 V
Analog I/O Voltage to AGND −0.3 V to VDD + 0.3 V ESD CAUTION
Operating Temperature Range
Industrial (B Version) −40°C to +125°C
Storage Temperature Range −65°C to +150°C
Maximum Junction Temperature 150°C
Lead Temperature, Soldering (10 sec) 300°C
IR Reflow, Peak Temperature 220°C
Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
AD9837 Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
COMP 1 10 VOUT
VDD 2 9 AGND
AD9837
CAP/2.5V 3 TOP VIEW 8 FSYNC
DGND 4 (Not to Scale) 7 SCLK
MCLK 5 6 SDATA
09070-005
NOTES
1. CONNECT EXPOSED PAD
TO GROUND.
Figure 4. Pin Configuration
Table 5. Pin Function Descriptions

Pin No. Mnemonic Description
1 COMP DAC Bias Pin. This pin is used for decoupling the DAC bias voltage.
2 VDD Positive Power Supply for the Analog and Digital Interface Sections. The on-board 2.5 V regulator is also
supplied from VDD. VDD can have a value from 2.3 V to 5.5 V. A 0.1 µF and a 10 µF decoupling capacitor should
be connected between VDD and AGND.
3 CAP/2.5V The digital circuitry operates from a 2.5 V power supply. This 2.5 V is generated from VDD using an on-board
regulator when VDD exceeds 2.7 V. The regulator requires a decoupling capacitor of 100 nF typical, which is
connected from CAP/2.5V to DGND. If VDD is less than or equal to 2.7 V, CAP/2.5V should be tied directly to
VDD to bypass the on-board regulator.
4 DGND Digital Ground.
5 MCLK Digital Clock Input. DDS output frequencies are expressed as a binary fraction of the frequency of MCLK. The
output frequency accuracy and phase noise are determined by this clock.
6 SDATA Serial Data Input. The 16-bit serial data-word is applied to this input.
7 SCLK Serial Clock Input. Data is clocked into the AD9837 on each falling edge of SCLK.
8 FSYNC Active Low Control Input. FSYNC is the frame synchronization signal for the input data. When FSYNC is taken
low, the internal logic is informed that a new word is being loaded into the device.
9 AGND Analog Ground.
10 VOUT Voltage Output. The analog and digital output from the AD9837 is available at this pin. An external load
resistor is not required because the device has a 200 Ω resistor on board.
EP Exposed Pad. Connect the exposed pad to ground.
Data Sheet AD9837
TYPICAL PERFORMANCE CHARACTERISTICS

5.0 –98
4.8
–99
4.6
4.4 VDD = 5V
–100
4.2
SFDR (dB)
IDD (mA)
4.0 VDD = 3V –101
3.8
–102
3.6
3.4
–103
3.2
3.0 –104
09070-009
09070-006
0 2 4 6 8 10 12 14 16 18 0 2 4 6 8 10 12 14 16 18
MCLK FREQUENCY (MHz) MCLK FREQUENCY (MHz)
Figure 5. Typical Current Consumption (IDD) vs. MCLK Frequency Figure 8. Narrow-Band SFDR vs. MCLK Frequency,
for fOUT = MCLK/10 fOUT = MCLK/50 to ±200 kHz
4.5 –50
4.4
VDD = 5V –55
4.3
MCLK/7
SFDR (dB)
4.2
IDD (mA)
–60
4.1
4.0
VDD = 3V –65
3.9 MCLK/50
3.8 –70
09070-007
09070-010
1 10 100 1000 1 3 5 7 9 11 13 15
OUTPUT FREQUENCY (kHz) MCLK FREQUENCY (MHz)
Figure 6. Typical IDD vs. Output Frequency for fMCLK = 5 MHz Figure 9. Wideband SFDR vs. MCLK Frequency
4.9
–56
4.8
VDD = 5V
–58
4.7
4.6 –60
SNR (dB)
IDD (mA)
4.5 –62
4.4
–64
4.3 VDD = 3V
–66
4.2
–68
4.1
–70
09070-011
4.0
09070-008
1 10 100 1k 10k 0 2 4 6 8 10 12 14 16 18
OUTPUT FREQUENCY (kHz) MCLK FREQUENCY (MHz)
Figure 7. Typical IDD vs. Output Frequency for fMCLK = 16 MHz Figure 10. SNR vs. MCLK Frequency
AD9837 Data Sheet
1000 0
–10
900
–20
VDD = 2.3V –30

WAKE-UP TIME (µs)
800
POWER (dB)
–40
VDD = 5.5V
700 –50
–60
600
–70
–80
500
–90
400 –100
09070-015
09070-012
–40 –20 0 20 40 60 80 100 120 140 0 10 20 30 40 50 60 70 80 90 100
TEMPERATURE (°C) FREQUENCY (kHz)
Figure 11. Wake-Up Time vs. Temperature Figure 14. Power vs. Frequency, fMCLK = 16 MHz, fOUT = 7.692 kHz,
Frequency Word = 0x1F81A
1.180 0
–10
1.178
VDD = 2.7V –20
1.176
VDD = 5.0V –30
1.174
POWER (dB)
–40
VREF (V)
1.172 –50
–60
1.170
–70
1.168
–80
1.166
–90
1.164 –100
09070-013
09070-016
–40 –20 0 20 40 60 80 100 120 140 0 0.5 1.0 1.5 2.0 2.5
TEMPERATURE (°C) FREQUENCY (MHz)
Figure 12. VREF vs. Temperature Figure 15. Power vs. Frequency, fMCLK = 5 MHz, fOUT = 0.714285 MHz = fMCLK/7,
Frequency Word = 0x2492492
0 0
–10 –10
–20 –20
–30 –30
POWER (dB)
POWER (dB)
–40 –40
–50 –50
–60 –60
–70 –70
–80 –80
–90 –90
–100 –100
09070-017
09070-014
0 10 20 30 40 50 60 70 80 90 100 0 1 2 3 4
FREQUENCY (kHz) FREQUENCY (MHz)
Figure 13. Power vs. Frequency, fMCLK = 5 MHz, fOUT = 2.4 kHz, Figure 16. Power vs. Frequency, fMCLK = 16 MHz, fOUT = 2.285714 MHz = fMCLK/7,
Frequency Word = 0x1F751 Frequency Word = 0x2492492
Data Sheet AD9837
TEST CIRCUIT
100nF
VDD
10nF
CAP/2.5V COMP
REGULATOR 12
SIN VOUT
10-BIT DAC
ROM
20pF
AD9837
09070-002
Figure 17. Test Circuit Used to Test Specifications
AD9837 Data Sheet
TERMINOLOGY
Integral Nonlinearity (INL) Total Harmonic Distortion (THD)
INL is the maximum deviation of any code from a straight line Total harmonic distortion (THD) is the ratio of the rms sum of
passing through the endpoints of the transfer function. The harmonics to the rms value of the fundamental. For the AD9837,
endpoints of the transfer function are zero scale, a point 0.5 LSB THD is defined as
below the first code transition (000 … 00 to 000 … 01), and full
scale, a point 0.5 LSB above the last code transition (111 … 10 V2 2 + V3 2 + V4 2 + V5 2 + V6 2
THD = 20 log
to 111 … 11). The error is expressed in LSBs. V1
Differential Nonlinearity (DNL) where:
DNL is the difference between the measured and ideal 1 LSB V1 is the rms amplitude of the fundamental.
change between two adjacent codes in the DAC. A specified V2, V3, V4, V5, and V6 are the rms amplitudes of the second
DNL of ±1 LSB maximum ensures monotonicity. through sixth harmonics.
Output Compliance Signal-to-Noise Ratio (SNR)
Output compliance refers to the maximum voltage that can be SNR is the ratio of the rms value of the measured output signal
generated at the output of the DAC to meet the specifications. to the rms sum of all other spectral components below the
When voltages greater than that specified for the output compli- Nyquist frequency. The value for SNR is expressed in decibels.
ance are generated, the AD9837 may not meet the specifications Clock Feedthrough
listed in the data sheet.
There is feedthrough from the MCLK input to the analog
Spurious-Free Dynamic Range (SFDR) output. Clock feedthrough refers to the magnitude of the
Along with the frequency of interest, harmonics of the funda- MCLK signal relative to the fundamental frequency in the
mental frequency and images of these frequencies are present at output spectrum of the AD9837.
the output of a DDS device. The spurious-free dynamic range
(SFDR) refers to the largest spur or harmonic present in the
band of interest. The wideband SFDR gives the magnitude of
the largest spur or harmonic relative to the magnitude of the
fundamental frequency in the 0 to Nyquist bandwidth. The
narrow-band SFDR gives the attenuation of the largest spur or
harmonic in a bandwidth of ±200 kHz about the fundamental
frequency.
Data Sheet AD9837
THEORY OF OPERATION
Sine waves are typically thought of in terms of their magnitude Solving for f and substituting the reference clock frequency for
form: a(t) = sin(ωt). However, sine waves are nonlinear and not the reference period (1/fMCLK = Δt),
easy to generate except through piecewise construction. On the f = ΔPhase × fMCLK∕2π (3)
other hand, the angular information is linear in nature; that is,
the phase angle rotates through a fixed angle for each unit of The AD9837 builds the output based on this simple equation. A
time. The angular rate depends on the frequency of the signal simple DDS chip can implement this equation with three major
by the traditional rate of ω = 2πf. subcircuits: numerically controlled oscillator (NCO) plus phase
modulator, SIN ROM, and digital-to-analog converter (DAC).
MAGNITUDE
+1 Each subcircuit is described in the Circuit Description section.
6π The AD9837 provides a sampled signal with its output following
0
2π 4π the Nyquist sampling theorem. Specifically, its output spectrum
contains the fundamental plus aliased signals (images) that occur
–1
at multiples of the reference clock frequency and the selected
PHASE output frequency. A graphical representation of the sampled
2π 4π 6π
228 spectrum with aliased images is shown in Figure 19.
The prominence of the aliased images depends on the ratio of
09070-023
0 fOUT to MCLK. If the ratio is small, the aliased images are very
Figure 18. Sine Wave prominent and of a relatively high energy level as determined by
Knowing that the phase of a sine wave is linear and given a the sin(x)/x roll-off of the quantized DAC output. In fact, depend-
reference interval (clock period), the phase rotation for that ing on the fOUT/reference clock ratio, the first aliased image can
period can be determined as follows: be on the order of −3 dB below the fundamental.
ΔPhase = ωΔt (1) External filtering is required if the aliased image is within the
output band of interest.
Solving for ω,
ω = ΔPhase/Δt = 2πf (2)
fOUT
sin(x)/x ENVELOPE
x = π (f/fC)
SIGNAL AMPLITUDE
fC – fOUT
fC + fOUT 2fC – fOUT
2fC + fOUT 3fC – fOUT

fC
2fC
3fC + fOUT
3 fC
0Hz FIRST SECOND THIRD FOURTH FIFTH SIXTH

IMAGE IMAGE IMAGE IMAGE IMAGE IMAGE
09070-040
SYSTEM CLOCK
FREQUENCY (Hz)
Figure 19. DAC Output Spectrum
AD9837 Data Sheet
CIRCUIT DESCRIPTION
The AD9837 is a fully integrated direct digital synthesis (DDS) SIN ROM
chip. The chip requires a reference clock and decoupling capa- To make the output from the NCO useful, it must be converted
citors to provide digitally created sine waves up to 8 MHz. In from phase information into a sinusoidal value. Because phase
addition to the generation of this RF signal, the chip is fully information maps directly to amplitude, the SIN ROM uses the
capable of a broad range of simple and complex modulation digital phase information as an address to a lookup table and
schemes. These modulation schemes are fully implemented in converts the phase information into amplitude.
the digital domain, allowing accurate and simple realization
of complex modulation algorithms using DSP techniques. Although the NCO contains a 28-bit phase accumulator, the out-
put of the NCO is truncated to 12 bits. Using the full resolution
The internal circuitry of the AD9837 consists of the following of the phase accumulator is impractical and unnecessary because
main sections: a numerically controlled oscillator (NCO), a lookup table of 228 entries would be required. It is only necessary
frequency and phase modulators, SIN ROM, a digital-to-analog to have sufficient phase resolution such that the errors due to
converter, and a regulator. truncation are smaller than the resolution of the 10-bit DAC.
NUMERICALLY CONTROLLED OSCILLATOR PLUS Therefore, the SIN ROM must have two bits of phase resolution
PHASE MODULATOR more than the 10-bit DAC.
The AD9837 consists of two frequency select registers, a phase The SIN ROM is enabled using the MODE bit (Bit D1) in the
accumulator, two phase offset registers, and a phase offset adder. control register (see Table 16).
The main component of the NCO is a 28-bit phase accumulator. DIGITAL-TO-ANALOG CONVERTER (DAC)
Continuous time signals have a phase range of 0 to 2π. Outside
this range of numbers, the sinusoid functions repeat themselves The AD9837 includes a high impedance, current source, 10-bit
in a periodic manner. The digital implementation is no different. DAC. The DAC receives the digital words from the SIN ROM
The accumulator simply scales the range of phase numbers into and converts them into the corresponding analog voltages.
a multibit digital word. The phase accumulator in the AD9837 The DAC is configured for single-ended operation. An external
is implemented with 28 bits. Therefore, in the AD9837, 2π = 228. load resistor is not required because the device has an on-board
Likewise, the ΔPhase term is scaled into this range of numbers: 200 Ω resistor. The DAC generates an output voltage of 0.6 V p-p
0 < ΔPhase < 228 − 1 typical.
With these substitutions, Equation 3 becomes REGULATOR

f = ΔPhase × fMCLK∕228 (4) VDD provides the power supply required for the analog section
and the digital section of the AD9837. This supply can have a
where 0 < ΔPhase < 228 − 1. value of 2.3 V to 5.5 V.
The input to the phase accumulator can be selected from either The internal digital section of the AD9837 is operated at 2.5 V.
the FREQ0 register or the FREQ1 register and is controlled by An on-board regulator steps down the voltage applied at VDD
the FSEL bit in the control register. NCOs inherently generate to 2.5 V. When the applied voltage at the VDD pin of the AD9837
continuous phase signals, thus avoiding any output discontinuity is less than or equal to 2.7 V, the CAP/2.5V and VDD pins should
when switching between frequencies. be tied together to bypass the on-board regulator.
Following the NCO, a phase offset can be added to perform phase
modulation using the 12-bit phase registers. The contents of one
of these phase registers is added to the MSBs of the NCO. The
AD9837 has two phase registers; their resolution is 2π/4096.
Data Sheet AD9837
FUNCTIONAL DESCRIPTION
SERIAL INTERFACE LATENCY PERIOD
The AD9837 has a standard 3-wire serial interface that is A latency period is associated with each asynchronous write
compatible with the SPI, QSPI™, MICROWIRE®, and DSP operation in the AD9837. If a selected frequency or phase
interface standards. register is loaded with a new word, there is a delay of seven
Data is loaded into the device as a 16-bit word under the control or eight MCLK cycles before the analog output changes. The
of a serial clock input, SCLK. The timing diagram for this oper- delay can be seven or eight cycles, depending on the position
ation is given in Figure 3. of the MCLK rising edge when the data is loaded into the
destination register.
FSYNC is a level triggered input that acts as a frame synchroni-
zation and chip enable input. Data can be transferred into the CONTROL REGISTER
device only when FSYNC is low. To start the serial data transfer, The AD9837 contains a 16-bit control register that allows the
FSYNC should be taken low, observing the minimum FSYNC user to configure the operation of the AD9837. All control bits
to SCLK falling edge setup time, t7 (see Table 2). After FSYNC other than the MODE bit are sampled on the internal falling
goes low, serial data is shifted into the input shift register of the edge of MCLK.
device on the falling edges of SCLK for 16 clock pulses. FSYNC Figure 20 illustrates the functions of the control bits. Table 7
can be taken high after the 16th falling edge of SCLK, observing describes the individual bits of the control register. The different
the minimum SCLK falling edge to FSYNC rising edge time, t8. functions and the various output options of the AD9837 are
Alternatively, FSYNC can be kept low for a multiple of 16 SCLK described in more detail in the following sections.
pulses and then brought high at the end of the data transfer. In
this way, a continuous stream of 16-bit words can be loaded To inform the AD9837 that the contents of the control register
while FSYNC is held low; FSYNC goes high only after the 16th will be altered, Bit D15 and Bit D14 must be set to 0, as shown
SCLK falling edge of the last word loaded. in Table 6.
The SCLK can be continuous, or it can idle high or low between Table 6. Control Register Bits
write operations. In either case, it must be high when FSYNC D15 D14 D13 to D0
goes low (t11). 0 0 Control bits
For an example of how to program the AD9837, see the AN-1070
Application Note on the Analog Devices, Inc., website. The
AD9837 has the same register settings as the AD9833/AD9834.
SLEEP12
SLEEP1
SIN
ROM 0 (LOW POWER)
RESET PHASE 10-BIT DAC
MUX
ACCUMULATOR 1
(28-BIT)
MODE + OPBITEN
1 DIGITAL
MUX OUTPUT VOUT
DIVIDE 0 (ENABLE)
BY 2
DIV2
OPBITEN
09070-024
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

0 0 B28 HLB FSEL PSEL 0 RESET SLEEP1 SLEEP12 OPBITEN 0 DIV2 0 MODE 0
Figure 20. Function of Control Bits
AD9837 Data Sheet
Table 7. Control Register Bit Descriptions
Bit Bit Name Description
D13 B28 Two write operations are required to load a complete word into either of the frequency registers.
B28 = 1 allows a complete word to be loaded into a frequency register in two consecutive writes. The first write
contains the 14 LSBs of the frequency word, and the second write contains the 14 MSBs. The first two bits of each
16-bit word define the frequency register to which the word is loaded and should, therefore, be the same for both
consecutive writes. See Table 9 for the appropriate addresses. The write to the frequency register occurs after both
words have been loaded, so the register never holds an intermediate value. An example of a complete 28-bit write
is shown in Table 10. Note, however, that consecutive 28-bit writes to the same frequency register are not allowed;
to execute consecutive 28-bit writes, you must alternate between the frequency registers.
B28 = 0 configures the 28-bit frequency register to operate as two 14-bit registers, one containing the 14 MSBs and
the other containing the 14 LSBs. In this way, the 14 MSBs of the frequency word can be altered independently of
the 14 LSBs, and vice versa. To alter the 14 MSBs or the 14 LSBs, a single write is made to the appropriate frequency
address. Bit D12 (HLB) informs the AD9837 whether the bits to be altered are the 14 MSBs or the 14 LSBs.
D12 HLB This control bit allows the user to continuously load the MSBs or LSBs of a frequency register while ignoring the
remaining 14 bits. This is useful if the complete 28-bit resolution is not required. The HLB bit is used in conjunction
with the B28 bit (Bit D13). The HLB bit indicates whether the 14 bits to be loaded are transferred to the 14 MSBs or
the 14 LSBs of the addressed frequency register. Bit D13 (B28) must be set to 0 to change the MSBs or LSBs of a
frequency word separately. When Bit D13 (B28) is set to 1, the HLB bit is ignored.
HLB = 1 allows a write to the 14 MSBs of the addressed frequency register.
HLB = 0 allows a write to the 14 LSBs of the addressed frequency register.
D11 FSEL The FSEL bit defines whether the FREQ0 register or the FREQ1 register is used in the phase accumulator (see Table 8).
D10 PSEL The PSEL bit defines whether the PHASE0 register data or the PHASE1 register data is added to the output of the
phase accumulator (see Table 8).
D9 Reserved This bit should be set to 0.
D8 RESET This bit controls the reset function.
RESET = 1 resets internal registers to 0, which corresponds to an analog output of midscale.
RESET = 0 disables the reset function (see the Reset Function section).
D7 SLEEP1 This bit enables or disables the internal MCLK.
SLEEP1 = 1 disables the internal MCLK. The DAC output remains at its present value because the NCO is no longer
accumulating.
SLEEP1 = 0 enables the internal MCLK (see the Sleep Function section).
D6 SLEEP12 This bit powers down the on-chip DAC.
SLEEP12 = 1 powers down the on-chip DAC. This is useful when the AD9837 is used to output the MSB of the DAC data.
SLEEP12 = 0 implies that the DAC is active (see the Sleep Function section).
D5 OPBITEN This bit, in association with the MODE bit (Bit D1), controls the output at the VOUT pin (see Table 16).
OPBITEN = 1 causes the output of the DAC to no longer be available at the VOUT pin. Instead, the MSB (or MSB/2) of
the DAC data is connected to the VOUT pin. This output is useful as a coarse clock source. The DIV2 bit (Bit D3)
controls whether the VOUT pin outputs the MSB or the MSB/2.
OPBITEN = 0 connects the output of the DAC to VOUT. The MODE bit (Bit D1) determines whether the output is
sinusoidal or triangular.
D4 Reserved This bit must be set to 0.
D3 DIV2 DIV2 is used in association with Bit D5 (OPBITEN). See Table 16.
DIV2 = 1 causes the MSB of the DAC data to be output at the VOUT pin.
DIV2 = 0 causes the MSB/2 of the DAC data to be output at the VOUT pin.
D1 MODE This bit, in association with the OPBITEN bit (Bit D5), controls the output at the VOUT pin when the on-chip DAC is
connected to VOUT. This bit should be set to 0 if the OPBITEN bit is set to 1 (see Table 16).
MODE = 1 bypasses the SIN ROM, resulting in a triangle output from the DAC.
MODE = 0 uses the SIN ROM to convert the phase information into amplitude information, resulting in a sinusoidal
signal at the output. (The OPBITEN bit (Bit D5) must also be set to 0 for sinusoidal output.)
Data Sheet AD9837
FREQUENCY AND PHASE REGISTERS Table 10. Writing 0xFFFC000 to the FREQ0 Register
The AD9837 contains two frequency registers and two phase SDATA Input Result of Input Word
registers, which are described in Table 8. 0010 0000 0000 0000 Control word write
(D15, D14 = 00), B28 (D13) = 1,
Table 8. Frequency and Phase Registers HLB (D12) = X
Register Size Description 0100 0000 0000 0000 FREQ0 register write
(D15, D14 = 01), 14 LSBs = 0x0000
FREQ0 28 bits Frequency Register 0.
When the FSEL bit = 0, the FREQ0 0111 1111 1111 1111 FREQ0 register write
register defines the output frequency (D15, D14 = 01), 14 MSBs = 0x3FFF
as a fraction of the MCLK frequency. Note, however, that continuous writes to the same frequency
FREQ1 28 bits Frequency Register 1. register may result in intermediate updates during the writes. If
When the FSEL bit = 1, the FREQ1 a frequency sweep, or something similar, is required, it is recom-
register defines the output frequency
as a fraction of the MCLK frequency. mended that users alternate between the two frequency registers.
PHASE0 12 bits Phase Offset Register 0. In some applications, the user does not need to alter all 28 bits
When the PSEL bit = 0, the contents of of the frequency register. With coarse tuning, only the 14 MSBs
the PHASE0 register are added to the are altered; with fine tuning, only the 14 LSBs are altered. By
output of the phase accumulator.
setting the B28 control bit (Bit D13) to 0, the 28-bit frequency
PHASE1 12 bits Phase Offset Register 1.
When the PSEL bit = 1, the contents of
register operates as two 14-bit registers, one containing the
the PHASE1 register are added to the 14 MSBs and the other containing the 14 LSBs. In this way, the
output of the phase accumulator. 14 MSBs of the frequency word can be altered independently
of the 14 LSBs, and vice versa. The HLB bit (Bit D12) in the
The analog output from the AD9837 is
control register identifies which 14 bits are being altered (see
fMCLK/228 × FREQREG Table 11 and Table 12).
where FREQREG is the value loaded into the selected frequency
Table 11. Writing 0x3FFF to the 14 LSBs of the FREQ1 Register
register.
SDATA Input Result of Input Word
This signal is phase shifted by 0000 0000 0000 0000 Control word write
2π/4096 × PHASEREG (D15, D14 = 00), B28 (D13) = 0,
HLB (D12) = 0, that is, LSBs
where PHASEREG is the value contained in the selected phase 1011 1111 1111 1111 FREQ1 register write
register. (D15, D14 = 10), 14 LSBs = 0x3FFF
The relationship of the selected output frequency and the refer-
Table 12. Writing 0x00FF to the 14 MSBs of the FREQ0 Register
ence clock frequency must be considered to avoid unwanted
output anomalies. SDATA Input Result of Input Word
0001 0000 0000 0000 Control word write
The flowchart in Figure 24 shows the routine for writing to the (D15, D14 = 00), B28 (D13) = 0,
frequency and phase registers of the AD9837. HLB (D12) = 1, that is, MSBs
Writing to a Frequency Register 0100 0000 1111 1111 FREQ0 register write
(D15, D14 = 01), 14 MSBs = 0x00FF
When writing to a frequency register, Bit D15 and Bit D14 of
the control register give the address of the frequency register Writing to a Phase Register
(see Table 9). When writing to a phase register, Bit D15 and Bit D14 are set to
11. Bit D13 identifies the phase register that is being loaded.
Table 9. Frequency Register Bits
D15 D14 D13 to D0 Table 13. Phase Register Bits
0 1 14 FREQ0 register bits D15 D14 D13 D12 D11 to D0
1 0 14 FREQ1 register bits 1 1 0 X 12 PHASE0 register bits
To change the entire contents of a frequency register, two consec- 1 1 1 X 12 PHASE1 register bits
utive writes to the same address must be performed because the
frequency registers are 28 bits wide. The first write contains the
14 LSBs, and the second write contains the 14 MSBs. For this
mode of operation, the B28 control bit (Bit D13) must be set
to 1. An example of a 28-bit write is shown in Table 10.
AD9837 Data Sheet
RESET FUNCTION The OPBITEN and MODE bits (Bit D5 and Bit D1 in the
control register) are used to determine the output that is
The reset function resets the appropriate internal registers to 0 available from the AD9837 (see Table 16).
to provide an analog output of midscale. A reset does not reset
the phase, frequency, or control registers. When the AD9837 is Table 16. Outputs from the VOUT Pin
powered up, the part should be reset (see the Powering Up the OPBITEN Bit MODE Bit DIV2 Bit VOUT Pin Output
AD9837 section). To reset the AD9837, set the RESET bit to 1. 0 0 X Sinusoid
To take the part out of reset, set the bit to 0. A signal appears at 0 1 X Triangle
the DAC output seven or eight MCLK cycles after the RESET 1 0 0 DAC data MSB/2
bit is set to 0. 1 0 1 DAC data MSB
1 1 X Reserved
Table 14. Applying the Reset Function
RESET Bit Result MSB of the DAC Data
0 No reset applied The MSB of the DAC data can be output from the AD9837. By
1 Internal registers reset setting the OPBITEN bit (Bit D5) to 1, the MSB of the DAC data
SLEEP FUNCTION is available at the VOUT pin. This is useful as a coarse clock
source. This square wave can also be divided by 2 before being
Sections of the AD9837 that are not in use can be powered
output. The DIV2 bit (Bit D3) in the control register controls
down to minimize power consumption by using the sleep
the frequency of this output from the VOUT pin.
function. The parts of the chip that can be powered down are
the internal clock and the DAC. The bits required for the sleep Sinusoidal Output
function are shown in Table 15. The SIN ROM converts the phase information from the frequency
and phase registers into amplitude information, resulting in a
Table 15. Applying the Sleep Function
sinusoidal signal at the output. To obtain a sinusoidal output
SLEEP1 Bit SLEEP12 Bit Result
from the VOUT pin, set the MODE bit (Bit D1) to 0 and the
0 0 No power-down OPBITEN bit (Bit D5) to 0.
0 1 DAC powered down
1 0 Internal clock disabled Triangle Output
1 1 DAC powered down and The SIN ROM can be bypassed so that the truncated digital output
internal clock disabled from the NCO is sent to the DAC. In this case, the output is no
DAC Powered Down longer sinusoidal. The DAC produces a 10-bit linear triangular
function (see Figure 21). To obtain a triangle output from the
When the AD9837 is used to output the MSB of the DAC data
VOUT pin, set the MODE bit (Bit D1) to 1 and the OPBITEN
only, the DAC is not required. The DAC can be powered down
bit (Bit D5) to 0.
using the SLEEP12 bit to reduce power consumption.
VOUT MAX
Internal Clock Disabled
When the internal clock of the AD9837 is disabled, the DAC
09070-025
VOUT MIN
output remains at its present value because the NCO is no 2π 4π 6π
longer accumulating. New frequency, phase, and control words
Figure 21. Triangle Output
can be written to the part when the SLEEP1 control bit is active.
Because the synchronizing clock (FSYNC) remains active, the POWERING UP THE AD9837
selected frequency and phase registers can also be changed using The flowchart in Figure 22 shows the operating routine for the
the control bits. Setting the SLEEP1 bit to 0 enables the MCLK. AD9837. When the AD9837 is powered up, the part should be
Any changes made to the registers while SLEEP1 was active are reset. This resets the appropriate internal registers to 0 to provide
observed at the output after a latency period (see the Latency an analog output of midscale. To avoid spurious DAC outputs
Period section). during AD9837 initialization, the RESET bit should be set to 1
VOUT PIN until the part is ready to begin generating an output.
The AD9837 offers a variety of outputs from the chip, all of A reset does not reset the phase, frequency, or control registers.
which are available from the VOUT pin. The available outputs These registers will contain invalid data and, therefore, should
are the MSB of the DAC data, a sinusoidal output, or a triangle be set to known values by the user. The RESET bit should then
output. be set to 0 to begin generating an output. The data appears on
the DAC output seven or eight MCLK cycles after the RESET
bit is set to 0.
Data Sheet AD9837
DATA WRITE
(SEE FIGURE 24)
SELECT DATA
SOURCES
WAIT 7/8 MCLK INITIALIZATION

CYCLES (SEE FIGURE 23)
YES YES
CHANGE
CHANGE PHASE?
PSEL BIT?
NO NO
YES CHANGE YES CHANGE PHASE

CHANGE FREQUENCY?
FSEL BIT? REGISTER?
NO NO YES
YES CHANGE FREQUENCY CHANGE DAC OUTPUT

REGISTER? FROM SIN TO TRIANGLE?
YES
NO
YES CHANGE OUTPUT TO

CONTROL REGISTER
WRITE A DIGITAL SIGNAL?
09070-026
(SEE TABLE 7)
NO
Figure 22. Flowchart for AD9837 Initialization and Operation
INITIALIZATION
APPLY RESET
(CONTROL REGISTER WRITE)
RESET = 1
WRITE TO FREQUENCY AND PHASE REGISTERS

FREQ0 REG = fOUT0/fMCLK × 228
FREQ1 REG = fOUT1/fMCLK × 228
PHASE0 AND PHASE1 REG = (PHASESHIFT × 212)/2π
(SEE FIGURE 24)
SET RESET = 0
SELECT FREQUENCY REGISTERS
SELECT PHASE REGISTERS
(CONTROL REGISTER WRITE)
RESET BIT = 0
09070-027
FSEL = SELECTED FREQUENCY REGISTER

PSEL = SELECTED PHASE REGISTER
Figure 23. Flowchart for Initialization
AD9837 Data Sheet
DATA WRITE
WRITE A FULL 28-BIT WORD NO WRITE 14 MSBs OR LSBs NO WRITE TO PHASE

TO A FREQUENCY REGISTER? TO A FREQUENCY REGISTER? REGISTER?
YES YES YES
(CONTROL REGISTER WRITE) (CONTROL REGISTER WRITE)

B28 (D13) = 0
B28 (D13) = 1 HLB (D12) = 0/1
(16-BIT WRITE)
D15, D14 = 11
D13 = 0/1 (CHOOSE THE
WRITE TWO CONSECUTIVE WRITE A 16-BIT WORD PHASE REGISTER)
16-BIT WORDS D12 = X
(SEE TABLE 11 AND TABLE 12 D11 ... D0 = PHASE DATA
(SEE TABLE 10 FOR EXAMPLE) FOR EXAMPLES)
WRITE ANOTHER FULL WRITE 14 MSBs OR LSBs WRITE TO ANOTHER

28-BIT WORD TO A TO A PHASE REGISTER? YES
FREQUENCY REGISTER? FREQUENCY REGISTER? YES
YES
09070-028
NO NO
NO
Figure 24. Flowchart for Data Writes
Data Sheet AD9837
APPLICATIONS INFORMATION
The various output options available from the AD9837 make Good decoupling is important. The AD9837 should have supply
the part suitable for a wide variety of applications, including bypassing of 0.1 μF ceramic capacitors in parallel with 10 μF
modulation applications. The AD9837 can be used to perform tantalum capacitors. To achieve the best performance from the
simple modulation, such as frequency shift keying (FSK). More decoupling capacitors, they should be placed as close as possible
complex modulation schemes, such as Gaussian minimum shift to the device, ideally right up against the device.
keying (GMSK) and quadrature phase shift keying (QPSK), can
INTERFACING TO MICROPROCESSORS
also be implemented using the AD9837.
The AD9837 has a standard serial interface that allows the part to
In an FSK application, the two frequency registers of the AD9837 interface directly with several microprocessors. The device uses
are loaded with different values. One frequency represents the an external serial clock to write the data or control information
space frequency, and the other represents the mark frequency. into the device. The serial clock can have a frequency of 40 MHz
Using the FSEL bit in the control register of the AD9837, the user maximum. The serial clock can be continuous, or it can idle high
can modulate the carrier frequency between the two values. or low between write operations. When data or control informa-
The AD9837 has two phase registers, enabling the part to per- tion is written to the AD9837, FSYNC is taken low and is held
form phase shift keying (PSK). With PSK, the carrier frequency low until the 16 bits of data are written into the AD9837. The
is phase shifted, that is, the phase is altered by an amount that FSYNC signal frames the 16 bits of information that are loaded
is related to the bit stream input to the modulator. into the AD9837.
The AD9837 is also suitable for signal generator applications. AD9837 to 68HC11/68L11 Interface
Because the MSB of the DAC data is available at the VOUT pin, Figure 25 shows the serial interface between the AD9837 and
the device can be used to generate a square wave. the 68HC11/68L11 microcontroller. The microcontroller is con-
With its low current consumption, the part is also suitable for figured as the master by setting the MSTR bit in the SPCR to 1.
applications in which it can be used as a local oscillator. This setting provides a serial clock on SCK; the MOSI output
drives the serial data line, SDATA. Because the microcontroller
GROUNDING AND LAYOUT
does not have a dedicated frame sync pin, the FSYNC signal is
The printed circuit board that houses the AD9837 should be derived from a port line (PC7). The setup conditions for correct
designed so that the analog and digital sections are separated operation of the interface are as follows:
and confined to certain areas of the board. This facilitates the use
of ground planes that can be separated easily. A minimum etch • SCK idles high between write operations (CPOL = 0)
technique is generally best for ground planes because it provides • Data is valid on the SCK falling edge (CPHA = 1)
the best shielding. Digital and analog ground planes should be When data is to be transmitted to the AD9837, the FSYNC line
joined in one place only. If the AD9837 is the only device that (PC7) is taken low. Serial data from the 68HC11/68L11 is trans-
requires an AGND to DGND connection, the ground planes mitted in 8-bit bytes with only eight falling clock edges occurring
should be connected at the AGND and DGND pins of the in the transmit cycle. Data is transmitted MSB first. To load data
AD9837. If the AD9837 is in a system where multiple devices into the AD9837, PC7 is held low after the first eight bits are
require AGND to DGND connections, the connection should transferred, and a second serial write operation is performed to
be made at one point only, a star ground point that should be the AD9837. Only after the second eight bits are transferred
established as close as possible to the AD9837. should FSYNC be taken high again.
Avoid running digital lines under the device; these lines couple
noise onto the die. The analog ground plane should be allowed 68HC11/68L11
AD9837
to run under the AD9837 to avoid noise coupling. The power
supply lines to the AD9837 should use as large a track as possible
to provide low impedance paths and reduce the effects of glitches PC7 FSYNC
SDATA
on the power supply line. Fast switching signals, such as clocks, MOSI
should be shielded with digital ground to avoid radiating noise SCK SCLK
09070-030
to other sections of the board.

Avoid crossover of digital and analog signals. Traces on opposite Figure 25. 68HC11/68L11 to AD9837 Interface
sides of the board should run at right angles to each other to
reduce the effects of feedthrough through the board. A micro-
strip technique is by far the best but is not always possible with
a double-sided board. In this technique, the component side of
the board is dedicated to ground planes and signals are placed
on the other side.
AD9837 Data Sheet
AD9837 to 80C51/80L51 Interface AD9837 to DSP56002 Interface
Figure 26 shows the serial interface between the AD9837 and Figure 27 shows the interface between the AD9837 and the
the 80C51/80L51 microcontroller. The microcontroller is oper- DSP56002. The DSP56002 is configured for normal mode asyn-
ated in Mode 0 so that TxD of the 80C51/80L51 drives SCLK of chronous operation with a gated internal clock (SYN = 0, GCK = 1,
the AD9837, and RxD drives the serial data line, SDATA. The SCKD = 1). The frame sync pin is generated internally (SC2 = 1),
FSYNC signal is derived from a bit programmable pin on the the transfers are 16 bits wide (WL1 = 1, WL0 = 0), and the frame
port (P3.3 is shown in Figure 26). sync signal frames the 16 bits (FSL = 0). The frame sync signal is
When data is to be transmitted to the AD9837, P3.3 is taken low. available on the SC2 pin, but it must be inverted before it is applied
The 80C51/80L51 transmits data in 8-bit bytes with only eight to the AD9837. The interface to the DSP56000/DSP56001 is
falling SCLK edges occurring in each cycle. To load the remain- similar to that of the DSP56002.
ing eight bits to the AD9837, P3.3 is held low after the first eight
bits are transmitted, and a second write operation is initiated to DSP56002
AD9837
transmit the second byte of data. P3.3 is taken high following
the completion of the second write operation. SCLK should idle SC2 FSYNC
high between the two write operations. STD SDATA
The 80C51/80L51 outputs the serial data in a format that has the SCK SCLK
LSB first. The AD9837 accepts the MSB first (the four MSBs are
09070-032
the control information, the next four bits are the address, and
the eight LSBs contain the data when writing to a destination Figure 27. DSP56002 to AD9837 Interface
register). Therefore, the transmit routine of the 80C51/80L51
must take this into account and rearrange the bits so that the
MSB is output first.
80C51/80L51
AD9837
P3.3 FSYNC
RxD SDATA
TxD SCLK
09070-031
Figure 26. 80C51/80L51 to AD9837 Interface
Data Sheet AD9837
EVALUATION BOARD
The AD9837 evaluation board allows designers to evaluate the
high performance AD9837 DDS modulator with a minimum
of effort.
SYSTEM DEMONSTRATION PLATFORM
The system demonstration platform (SDP) is a hardware and
software evaluation tool for use in conjunction with product
evaluation boards. The SDP board is based on the Blackfin®
ADSP-BF527 processor with USB connectivity to the PC
through a USB 2.0 high speed port. For more information,
see the SDP board product page.
Note that the SDP board is sold separately from the AD9837
evaluation board.
AD9837 TO SPORT INTERFACE
The Analog Devices SDP board has a SPORT serial port that is
09070-037
used to control the serial inputs to the AD9837. The connections
are shown in Figure 28. Figure 29. AD9837 Evaluation Software Interface
ADSP-BF527
AD9837
CRYSTAL OSCILLATOR VS. EXTERNAL CLOCK
The AD9837 can operate with master clocks up to 16 MHz.
SPORT_TFS FSYNC
A 16 MHz oscillator is included on the evaluation board. This
SPORT_TSCLK SCLK oscillator can be removed and, if required, an external CMOS
SPORT_DT0 SDATA
clock can be connected to the part. Options for the general
oscillator include the following:
09070-033
• AEL 301-Series oscillators, AEL Crystals

Figure 28. SDP to AD9837 Interface • SG-310SCN oscillators, Epson Electronics
EVALUATION KIT POWER SUPPLY
The DDS evaluation kit includes a populated, tested AD9837 Power to the AD9837 evaluation board can be provided from
printed circuit board (PCB). The schematics of the evaluation the USB connector or externally through pin connections. The
board are shown in Figure 30 and Figure 31. power leads should be twisted to reduce ground loops.
The software provided in the evaluation kit allows the user to
easily program the AD9837 (see Figure 29). The evaluation soft-
ware runs on any IBM-compatible PC with Microsoft® Windows®
software installed (including Windows 7). The software is com-
patible with both 32-bit and 64-bit operating systems.
More information about the evaluation software is available on
the software CD and on the AD9837 product page.
AD9837 Data Sheet
EVALUATION BOARD SCHEMATICS
09070-034
Figure 30. Evaluation Board Schematic
Data Sheet AD9837
09070-038
Figure 31. SDP Connector Schematic
AD9837 Data Sheet
EVALUATION BOARD LAYOUT
09070-039
Figure 32. Evaluation Board Layout
Data Sheet AD9837
OUTLINE DIMENSIONS
2.48
2.38
3.10
2.23
3.00 SQ
2.90 0.50 BSC
6 10
PIN 1 INDEX EXPOSED 1.74

AREA PAD
1.64
0.50 1.49
0.40
0.30 5
1 PIN 1
TOP VIEW BOTTOM VIEW INDICATOR
(R 0.15)
0.80 FOR PROPER CONNECTION OF

0.75 0.05 MAX THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
0.70 0.02 NOM FUNCTION DESCRIPTIONS
COPLANARITY SECTION OF THIS DATA SHEET.
SEATING 0.08
02-27-2012-B
0.30
PLANE 0.25 0.20 REF
0.20
Figure 33. 10-Lead Lead Frame Chip Scale Package [LFCSP_WD]

3 mm × 3 mm Body, Very Very Thin, Dual Lead
(CP-10-9)
Dimensions shown in millimeters
ORDERING GUIDE
Temperature Package
Model1, 2 Range Max MCLK Package Description Option Branding
AD9837BCPZ-RL −40°C to +125°C 16 MHz 10-Lead Lead Frame Chip Scale Package [LFCSP_WD] CP-10-9 DGH
AD9837BCPZ-RL7 −40°C to +125°C 16 MHz 10-Lead Lead Frame Chip Scale Package [LFCSP_WD] CP-10-9 DGH
AD9837ACPZ-RL −40°C to +125°C 5 MHz 10-Lead Lead Frame Chip Scale Package [LFCSP_WD] CP-10-9 DGG
AD9837ACPZ-RL7 −40°C to +125°C 5 MHz 10-Lead Lead Frame Chip Scale Package [LFCSP_WD] CP-10-9 DGG
EVAL-AD9837SDZ Evaluation Board
1
Z = RoHS Compliant Part.
2
The evaluation board for the AD9837 requires the system demonstration platform (SDP) board, which is sold separately.
AD9837 Data Sheet
NOTES
Data Sheet AD9837
NOTES
AD9837 Data Sheet
NOTES
©2011–2012 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D09070-0-12/12(A)
4
5
10
11
SBB
SRF
SOSC-RF
BB BB
BB SOSC-RF f
SA602A
Double-balanced mixer and oscillator
Rev. 3 — 27 May 2014 Product data sheet
1. General description
The SA602A is a low-power VHF monolithic double-balanced mixer with input amplifier,
on-board oscillator, and voltage regulator. It is intended for high-performance, low-power
communication systems. The guaranteed parameters of the SA602A make this device
well-suited for cellular radio applications. The mixer is a ‘Gilbert cell’ multiplier
configuration which typically provides 18 dB of gain at 45 MHz. The oscillator operates to
200 MHz. It can be configured as a crystal oscillator, a tuned tank oscillator, or a buffer for
an external LO. For higher frequencies, the LO input may be externally driven. The noise
figure at 45 MHz is typically less than 5 dB. The gain, intercept performance, low-power
and noise characteristics make the SA602A a superior choice for high-performance
battery operated equipment. It is available in an 8-lead SO (surface-mount miniature
package).
2. Features and benefits

 Low current consumption: 2.4 mA typical
 Excellent noise figure: <4.7 dB typical at 45 MHz
 High operating frequency
 Excellent gain, intercept and sensitivity
 Low external parts count; suitable for crystal/ceramic filters
 SA602A meets cellular radio specifications
3. Applications
 Cellular radio mixer/oscillator
 Portable radio
 VHF transceivers
 RF data links
 HF/VHF frequency conversion
 Instrumentation frequency conversion
 Broadband LANs
NXP Semiconductors SA602A
4. Ordering information
Table 1. Ordering information
Type number Package
Name Description Version
SA602AD/01 SO8 plastic small outline package; 8 leads; body width 3.9 mm SOT96-1
4.1 Ordering options

Table 2. Ordering options
Type number Orderable Package Packing method Minimum Temperature
part number order
quantity
SA602AD/01 SA602AD/01,112 SO8 Standard marking 2000 Tamb = 40 C to +85 C
* IC’s tube - DSC bulk pack
SA602AD/01,118 SO8 Reel 13” Q1/T1 2500 Tamb = 40 C to +85 C
Standard mark SMD
5. Block diagram
OSC_E
OSC_B
OUT_B
VCC
8 7 6 5
E B
VOLTAGE
REGULATOR OSCILLATOR
1 2 3 4
IN_A
OUT_A
IN_B
GND
aaa-013202
Fig 1. Block diagram
SA602A All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3 — 27 May 2014 2 of 19

6. Pinning information
6.1 Pinning
SA602AD/01
IN_A 1 8 VCC
IN_B 2 7 OSC_E
GND 3 6 OSC_B
OUT_A 4 5 OUT_B
aaa-013201
Fig 2. Pin configuration for SO8
6.2 Pin description

Table 3. Pin description
Symbol Pin Description
IN_A 1 RF input A
IN_B 2 RF input B
GND 3 ground
OUT_A 4 mixer output A
OUT_B 5 mixer output B
OSC_B 6 oscillator input (base)
OSC_E 7 oscillator output (emitter)
VCC 8 supply voltage

7. Functional description
The SA602A is a Gilbert cell, an oscillator/buffer, and a temperature-compensated bias
network as shown in Figure 3. The Gilbert cell is a differential amplifier (IN_A and IN_B
pins) that drives a balanced switching cell. The differential input stage provides gain and
determines the noise figure and signal handling performance of the system.
18 kΩ
1.5 kΩ 1.5 kΩ
buffer
6
4 5
7
25 kΩ
BIAS BIAS
2
1
BIAS
1.5 kΩ 1.5 kΩ
3
GND
aaa-013205
Fig 3. Equivalent circuit
The SA602A is designed for optimum low-power performance. When used with the
SA604A as a 45 MHz cellular radio second IF and demodulator, the SA602A is capable of
receiving 119 dBm signals with a 12 dB S/N ratio. Third-order intercept is typically
13 dBm (that is approximately +5 dBm output intercept because of the RF gain). The
system designer must be cognizant of this large signal limitation. When designing LANs or
other closed systems where transmission levels are high, and small-signal or
signal-to-noise issues are not critical, the input to the SA602A should be appropriately
scaled.
Besides excellent low-power performance well into VHF, the SA602A is designed to be
flexible. The input, RF mixer output and oscillator ports support various configurations
provided the designer understands certain constraints, which are explained here.
The RF inputs (IN_A and IN_B pins) are biased internally. They are symmetrical. The
equivalent AC input impedance is approximately 1.5 k  3 pF through 50 MHz. IN_A and
IN_B pins can be used interchangeably, but they should not be DC biased externally.
Figure 4 shows three typical input configurations.

SA602A SA602A SA602A
2
input
aaa-013216 aaa-013217 aaa-013218
a. Single-ended b. Balanced input c. Single-ended

tuned input (for attenuation of untuned input
second-order
products)
Fig 4. Input configuration
The mixer outputs (OUT_A and OUT_B pins) are also internally biased. Each output is
connected to the internal positive supply by a 1.5 k resistor. This permits direct output
termination yet allows for balanced output as well. Figure 5 shows three single-ended
output configurations and a balanced output.
5
5
SA602A SA602A
4
4
aaa-013219 aaa-013220
a. Single-ended ceramic filter b. Single-ended crystal filter

5
SA602A SA602A
4
aaa-013221 aaa-013222
c. Single-ended IFT d. Balanced output

Fig 5. Output configuration

The oscillator can sustain oscillation beyond 200 MHz in crystal or tuned tank
configurations. The upper limit of operation is determined by tank ‘Q’ and required drive
levels. The higher the ‘Q’ of the tank or the smaller the required drive, the higher the
permissible oscillation frequency. If the required LO is beyond oscillation limits, or the
system calls for an external LO, the external signal can be injected at OSC_B (pin 6)
through a DC blocking capacitor. External LO should be at least 200 mV (peak-to-peak).
Figure 6 shows several proven oscillator circuits. Figure 6a is appropriate for cellular
radio. As shown, an overtone mode of operation is utilized. Capacitor C3 and inductor L1
suppress oscillation at the crystal fundamental frequency. In the fundamental mode, the
suppression network is omitted.
C2
L1 C3 XTAL
C1
8
5
SA602A SA602A SA602A
1
4
aaa-013237 aaa-013238 aaa-013239
a. Colpitts crystal b. Colpitts L/C tank c. Hartley L/C tank

oscillator oscillator oscillator
(overtone mode)
Fig 6. Oscillator circuits
Figure 7 shows a Colpitts varactor tuned tank oscillator suitable for synthesizer-controlled
applications. It is important to buffer the output of this circuit to assure that switching
spikes from the first counter or prescaler do not end up in the oscillator spectrum. The
dual-gate MOSFET provides optimum isolation with low current. The FET offers good
isolation, simplicity, and low current, while the bipolar transistors provide the simple
solution for non-critical applications. The resistive divider in the emitter-follower circuit
should be chosen to provide the minimum input signal that assures correct system
operation.
When operated above 100 MHz, the oscillator may not start if the Q of the tank is too low.
A 22 k resistor from OSC_E (pin 7) to ground increases the DC bias current of the
oscillator transistor. This improves the AC operating characteristic of the transistor and
should help the oscillator to start. A 22 k resistor does not upset the other DC biasing
internal to the device, but smaller resistance values should be avoided.

5.5 μH
+6 V
10 nF 10 μF 0.1 μF
1 8
2 7 to buffer
SA602A 7 pF 10 pF
3 6
1000 pF
DC control voltage
4 5
1000 pF
from synthesizer
MV2105
0.06 μH or equivalent
0.01 μF
100 kΩ 2 kΩ
2N918
3SK126
2 pF
to synthesizer
2N5484
100 kΩ 330 Ω 0.01 μF to synthesizer
100 kΩ
1.0 nF
aaa-013258
Fig 7. Colpitts oscillator suitable for synthesizer applications and typical buffers
8. Application design-in information
22 pF
0.5 μH to
1.3 μH 44.545 MHz
1 nF
third overtone crystal
5.5 μH 10 pF
VCC
6.8 μF 100 nF 10 nF
8
SA602A
SFG455A3
1
or equivalent
output
47 pF 0.209 μH
45 MHz to
RF input 0.283 μH
220 pF
100 nF
aaa-013257
Fig 8. Typical application for cellular radio

9. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage - 9 V
Tstg storage temperature 65 +150 C
Tamb ambient temperature operating 40 +85 C
10. Thermal characteristics

Table 5. Thermal characteristics
Symbol Parameter Conditions Min Max Unit
Zth(j-a) transient thermal impedance - 90 C/W
from junction to ambient
11. Static characteristics

Table 6. Static characteristics
VCC = +6 V; Tamb = 25 C; unless specified otherwise.
Symbol Parameter Conditions Min Typ Max Unit
VCC supply voltage 4.5 - 8.0 V
ICC supply current - 2.4 2.8 mA
12. Dynamic characteristics

Table 7. Dynamic characteristics
Tamb = 25 C; VCC = +6 V; unless specified otherwise.
Symbol Parameter Conditions Min Typ Max Unit
fi input frequency - 500 - MHz
fosc oscillator frequency - 200 - MHz
NF noise figure at 45 MHz - 5.0 5.5 dB
IP3i input third-order RF input = 45 dBm; - 13 15 dBm
intercept point RF1 = 45.0 MHz;
RF2 = 45.06 MHz
Gconv conversion gain at 45 MHz 14 17 - dB
Ri(RF) RF input resistance 1.5 - - k
Ci(RF) RF input capacitance - 3 3.5 pF
Ro(mix) mixer output resistance OUT_A, OUT_B pins - 1.5 - k

13. Performance curves
aaa-013241 aaa-013242
3.5 20.0
ICC
(mA) Gconv
VCC = 8.5 V (dB)
3.0
VCC = 8.5 V
18.0
6.0 V
2.5 6.0 V 4.5 V
4.5 V 16.0
2.0
1.5 14.0
−40 −20 0 20 40 60 80 90 −40 −20 0 20 40 60 80 90
Tamb (°C) Tamb (°C)
Fig 9. Supply current versus temperature Fig 10. Conversion gain versus temperature
aaa-013243 aaa-013244
−10.0 6.0
NF
IP3i (dB)
(dBm)
5.5
−12.0 VCC = 8.5 V
6.0 V
5.0 4.5 V
−14.0
4.5
−16.0 4.0
−40 −20 0 20 40 60 80 90 −40 −20 0 20 40 60 80 90
Tamb (°C) Tamb (°C)
Fig 11. Third-order intercept point versus temperature Fig 12. Noise Figure versus temperature
aaa-013245 aaa-013246
40 −10
IP3i
IF output power third-order product
(dBm)
(dBm)
−12
0
−14
fund. product
−40
−16
−80 −18
−80 −60 −40 −20 0 20 4 6 8 10
RF input level (dBm) VCC (V)
RF1 = 45 MHz; IF = 455 kHz; RF2 = 45.06 MHz

Fig 13. Third-order intercept and compression Fig 14. Input third-order intercept point versus
supply voltage

14. Test information
22 pF
0.5 μH to
1.3 μH 44.545 MHz
1 nF
third overtone crystal
5.5 μH 10 pF
VCC
6.8 μF 100 nF 10 nF
5
330 pF
303 μH
455 kHz
IF output
SA602A to 560 pF
765 μH
100 nF
4
47 pF 0.209 μH
45 MHz to
RF input 0.283 μH
220 pF
100 nF
aaa-013203
Fig 15. Test configuration

15. Package outline
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Fig 16. Package outline SOT96-1 (SO8)


16. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
16.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
16.2 Wave and reflow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
• Board specifications, including the board finish, solder masks and vias
• Package footprints, including solder thieves and orientation
• The moisture sensitivity level of the packages
• Package placement
• Inspection and repair
• Lead-free soldering versus SnPb soldering
16.3 Wave soldering

Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities

16.4 Reflow soldering

Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 17) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 8 and 9
Table 8. SnPb eutectic process (from J-STD-020D)

Package thickness (mm) Package reflow temperature (C)
Volume (mm3)
< 350  350
< 2.5 235 220
 2.5 220 220
Table 9. Lead-free process (from J-STD-020D)

Package thickness (mm) Package reflow temperature (C)
Volume (mm3)
< 350 350 to 2000 > 2000
< 1.6 260 260 260
1.6 to 2.5 260 250 245
> 2.5 250 245 245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 17.

maximum peak temperature

temperature = MSL limit, damage level
minimum peak temperature

= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level

Fig 17. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365

“Surface mount reflow soldering description”.
17. Soldering: PCB footprints

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î
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Fig 18. PCB footprint for SOT96-1 (SO8); reflow soldering

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Fig 19. PCB footprint for SOT96-1 (SO8); wave soldering
18. Abbreviations
Table 10. Abbreviations
Acronym Description
FET Field-Effect Transistor
HF High Frequency
IF Intermediate Frequency
LAN Local Area Network
LO Local Oscillator
MOSFET Metal-Oxide Semiconductor Field-Effect Transistor
RF Radio Frequency
VHF Very High Frequency

19. Revision history

Table 11. Revision history
Document ID Release date Data sheet status Change notice Supersedes
SA602A v.3 20140527 Product data sheet - SA602A v.2
Modifications: • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP
Semiconductors.
• Legal texts have been adapted to the new company name where appropriate.
• Section 1 “General description”, last sentence: deleted “8-lead dual in-line plastic package”
• Table 1 “Ordering information”:
– Type number SA602AN (DIP8 package, SOT97-1 package outline) is discontinued and removed
from this data sheet
– Type number changed from “SA602AD” to “SA602AD/01”
• Added Section 4.1 “Ordering options”
• Added Section 6.2 “Pin description”
• Figure 7 “Colpitts oscillator suitable for synthesizer applications and typical buffers”:
capacitor value corrected from “0.10 pF” to “10 nF” (above pin 8)
• Figure 8 “Typical application for cellular radio”: component value corrected from “34.545 MHz third
overtone crystal” to “44.545 MHz third overtone crystal”
• Table 5 “Thermal characteristics”: deleted characteristic values for “N package” (SA602AN)
• Old table “AC/DC electrical characteristics” split into Table 6 “Static characteristics” and
Table 7 “Dynamic characteristics”
• Table 7 “Dynamic characteristics”, Conditions for IP3i, input third-order intercept point,
corrected from “f1” to “RF1” and from “f2” to “RF2”
• Figure 15 “Test configuration”: component values corrected throughout this drawing
• Package outline SOT97-1 (DIP8) is deleted
• Added soldering information
• Added Section 17 “Soldering: PCB footprints”
• Added Section 18 “Abbreviations”
SA602A v.2 19971107 Product specification 853-1424 18662 NE/SA602A v.1
NE/SA602A v.1 19900417 Product specification 853-1424 99374 -

20. Legal information
20.1 Data sheet status

Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
20.2 Definitions Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
Draft — The document is a draft version only. The content is still under
malfunction of an NXP Semiconductors product can reasonably be expected
internal review and subject to formal approval, which may result in
to result in personal injury, death or severe property or environmental
modifications or additions. NXP Semiconductors does not give any
damage. NXP Semiconductors and its suppliers accept no liability for
representations or warranties as to the accuracy or completeness of
inclusion and/or use of NXP Semiconductors products in such equipment or
information included herein and shall have no liability for the consequences of
applications and therefore such inclusion and/or use is at the customer’s own
use of such information.
risk.
Short data sheet — A short data sheet is an extract from a full data sheet
Applications — Applications that are described herein for any of these
with the same product type number(s) and title. A short data sheet is intended
products are for illustrative purposes only. NXP Semiconductors makes no
for quick reference only and should not be relied upon to contain detailed and
representation or warranty that such applications will be suitable for the
full information. For detailed and full information see the relevant full data
specified use without further testing or modification.
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the Customers are responsible for the design and operation of their applications
full data sheet shall prevail. and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
Product specification — The information and data provided in a Product design. It is customer’s sole responsibility to determine whether the NXP
data sheet shall define the specification of the product as agreed between Semiconductors product is suitable and fit for the customer’s applications and
NXP Semiconductors and its customer, unless NXP Semiconductors and products planned, as well as for the planned application and use of
customer have explicitly agreed otherwise in writing. In no event however, customer’s third party customer(s). Customers should provide appropriate
shall an agreement be valid in which the NXP Semiconductors product is design and operating safeguards to minimize the risks associated with their
deemed to offer functions and qualities beyond those described in the applications and products.
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
20.3 Disclaimers customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Limited warranty and liability — Information in this document is believed to
Semiconductors products in order to avoid a default of the applications and
be accurate and reliable. However, NXP Semiconductors does not give any
the products or of the application or use by customer’s third party
representations or warranties, expressed or implied, as to the accuracy or
customer(s). NXP does not accept any liability in this respect.
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no Limiting values — Stress above one or more limiting values (as defined in
responsibility for the content in this document if provided by an information the Absolute Maximum Ratings System of IEC 60134) will cause permanent
source outside of NXP Semiconductors. damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
In no event shall NXP Semiconductors be liable for any indirect, incidental,
the Recommended operating conditions section (if present) or the
punitive, special or consequential damages (including - without limitation - lost
Characteristics sections of this document is not warranted. Constant or
profits, lost savings, business interruption, costs related to the removal or
repeated exposure to limiting values will permanently and irreversibly affect
replacement of any products or rework charges) whether or not such
the quality and reliability of the device.
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory. Terms and conditions of commercial sale — NXP Semiconductors
Notwithstanding any damages that customer might incur for any reason products are sold subject to the general terms and conditions of commercial
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards sale, as published at http://www.nxp.com/profile/terms, unless otherwise
customer for the products described herein shall be limited in accordance agreed in a valid written individual agreement. In case an individual
with the Terms and conditions of commercial sale of NXP Semiconductors. agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
Right to make changes — NXP Semiconductors reserves the right to make applying the customer’s general terms and conditions with regard to the
changes to information published in this document, including without purchase of NXP Semiconductors products by customer.
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior No offer to sell or license — Nothing in this document may be interpreted or
to the publication hereof. construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.

Export control — This document as well as the item(s) described herein NXP Semiconductors’ specifications such use shall be solely at customer’s
may be subject to export control regulations. Export might require a prior own risk, and (c) customer fully indemnifies NXP Semiconductors for any
authorization from competent authorities. liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
Non-automotive qualified products — Unless this data sheet expressly
standard warranty and NXP Semiconductors’ product specifications.
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested Translations — A non-English (translated) version of a document is for
in accordance with automotive testing or application requirements. NXP reference only. The English version shall prevail in case of any discrepancy
Semiconductors accepts no liability for inclusion and/or use of between the translated and English versions.
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer 20.4 Trademarks
(a) shall use the product without NXP Semiconductors’ warranty of the
Notice: All referenced brands, product names, service names and trademarks
product for such automotive applications, use and specifications, and (b)
are the property of their respective owners.
whenever customer uses the product for automotive applications beyond
21. Contact information

For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com

22. Contents
1 General description . . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
4 Ordering information . . . . . . . . . . . . . . . . . . . . . 2
4.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2
5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2
6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
7 Functional description . . . . . . . . . . . . . . . . . . . 4
8 Application design-in information . . . . . . . . . . 7
9 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 8
10 Thermal characteristics . . . . . . . . . . . . . . . . . . 8
11 Static characteristics. . . . . . . . . . . . . . . . . . . . . 8
12 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8
13 Performance curves . . . . . . . . . . . . . . . . . . . . . 9
14 Test information . . . . . . . . . . . . . . . . . . . . . . . . 10
15 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11
16 Soldering of SMD packages . . . . . . . . . . . . . . 12
16.1 Introduction to soldering . . . . . . . . . . . . . . . . . 12
16.2 Wave and reflow soldering . . . . . . . . . . . . . . . 12
16.3 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 12
16.4 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 13
17 Soldering: PCB footprints. . . . . . . . . . . . . . . . 14
18 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 15
19 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 16
20 Legal information. . . . . . . . . . . . . . . . . . . . . . . 17
20.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17
20.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
20.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
20.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 18
21 Contact information. . . . . . . . . . . . . . . . . . . . . 18
22 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2014. All rights reserved.

For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 27 May 2014
Document identifier: SA602A
Mouser Electronics
Authorized Distributor
Click to View Pricing, Inventory, Delivery & Lifecycle Information:
NXP:
SA602AD/01,112 SA602AD/01,118
AA-230 ZOOM
AA-230 ZOOM Option BLE RigExpert ®
Antenna and cable analyzers
User’s manual
For latest manuals and software updates,
please visit
http://rigexpert.com
.
Table of contents
Introduction 4
Operating the AA-230 ZOOM 5
First time use 5
Main menu 5
Multifunctional keys 6
Connecting to your antenna 6
SWR chart 7
Chart ZOOM 7
Data screen 8
Frequency and range entry 8
Return loss chart 8
R,X chart 9
Smith chart 9
Memory operation 10
SWR mode 10
Display all parameters 11
MultiSWR mode 12
Applications 13
Antennas 13
Coaxial lines 14
Measurement of other elements 21
Annexes 24
Annex 1: Specifications 24
Annex 2: Precautions 25
Annex 3: Tools menu 26
Annex 4: Setup menu 31
Annex 5: TDR mode 32
Annex 6: Calibration 36
Annex 7: Dummy loads 38
Introduction
1
Thank you for purchasing a RigExpert
AA-230 ZOOM Antenna and Cable Analyzer! We
did our best to make it powerful yet easy to use.
The analyzer is designed for measuring SWR
(standing wave ratio), return loss, cable loss,
as well as other parameters of cable and
antenna systems in the range of 100 kHz to
230 MHz. A built-in ZOOM capability makes 2
graphical measurements especially effective.
An integrated Time Domain Reflectometer mode
can be used to locate a fault within the feedline
system.
The AA-230 ZOOM Option BLE version of the
analyzer is equipped with a Bluetooth Low 3
Energy module for a wireless connection with
your laptop, tablet or smartphone.
The following tasks are easily accomplished by

using this analyzer:
• Rapid check-out of an antenna
• Tuning an antenna to resonance
• Comparing characteristics of an antenna 4
before and after specific event (rain, hurricane,
etc.) 1. Antenna connector
• Making coaxial stubs or measuring their 2. Liquid crystal display
parameters 3. Keypad
• Cable testing and fault location, measuring 4. USB connector
cable loss and characteristic impedance
• Measuring capacitance or inductance of
reactive loads
4 User’s manual
First time use Operating the
AA-230 ZOOM
Please insert four AAA batteries
(either alkaline or Ni-MH ones)
into the battery compartment
of the analyzer, watching the
polarity. Instead, you may power it from a spare USB port of your computer by using a
conventional USB cable.
Press the (Power) key located at the bottom-right corner of the keypad to turn on
the analyzer. After displaying the initial message (showing a firmware version and a
serial number of the instrument), a Main menu appears on the screen.
The analyzer will be turned off automatically if not in use for too long.
Main menu
The Main menu acts as a starting point
from where different tasks may be
launched.
Use (Cursor up) and (Cursor

down) keys to scroll through the menu,
then press (OK) to select an item.
For your convenience, a battery
indicator is shown at the top-left corner
of the screen. This indicator is replaced
with a USB icon when the analyzer is
connected to your computer.
You may use hot keys for the quick access to certain tasks. For instance, press
the (SWR chart) button to open the SWR chart screen immediately.
RigExpert AA-230 ZOOM 5

Multifunctional keys
Most keys on the analyzer’s keypad perform
several functions. 3 1
For instance, numbers (1) are used to enter
frequency and other numerical parameters.
Main functions (2) provide quick access to most
common tasks. Alternative functions (3) are
executed if the user holds the (Functional) 2
key. For the convenience, alternative functions
are marked with yellow.
You may press the (Help) key to open a help screen listing all active hot keys.
Connecting to your antenna

Plug the cable to your analyzer’s antenna connector, and then tighten the rotating
sleeve. The rest of the connector, as well as the cable, should remain stationary.
If you twist other parts of the connector when tightening or loosening, damage may
easily occur. Twisting is not allowed by design of the N-connector.
6 User’s manual
SWR chart
Once your antenna is connected to
the analyzer, it is time to measure its
characteristics. Press the (SWR
chart) key to open the SWR chart screen,
then press (OK) to start a new
measurement.
A few moments later, the result will be
displayed on the analyzer’s screen.
Press the + key combination to

run a continuous sweep.
A small triangle at the bottom of the chart corresponds to a point at which the SWR
reaches its minimum.
Chart ZOOM
Use the arrow keys to increase or decrease the center frequency or the scanning range.
Watch the chart zooming in or out, or changing its position. Use the (Functional
key) and (Cursor up) or (Cursor down) key combination to zoom the vertical
scale of the chart.
Do not forget to press the (OK) key for the new measurement to start.
Press (Functional key) and to quickly choose a radio amateur band.

Data screen
The data screen is available in all chart
modes. Press the (Data) key to
display various parameters of a load at
cursor.
Frequency
and range entry
To enter the center frequency or the
sweep range, press the (Frequency,
Range) key.
Use cursor keys to navigate, or the

to keys to enter values. Do not forget
to press the (OK) key to apply.
Press (Up) or (Down) cursor keys while holding

the (Functional) key to quickly choose a radio amateur band.
Return loss chart

The return loss (RL) chart, which is very similar to the SWR chart, is activated by
pressing the (Functional key) and (RL chart) key combination in the Main
menu.
8 User’s manual
R,X chart
Press the (R,X chart) key in the Main
menu to access the R,X chart mode.
Positive values of reactance (X)

correspond to inductive load, while
negative values correspond to capacitive
load.
The chart will display R and X for series

or parallel models of a load. Press
(Functional key) and to switch
between these models.
The marker at the bottom of the screen shows a resonant

frequency closest to the center of the scan.
Smith chart
The (Smith chart) key opens a
screen where the reflection coefficient is
plotted on the Smith chart.
For a list of hot keys, press the

(Help) key, as usual.
A small marker is used to indicate the center frequency.

Memory operation
Press the (Save) key to save the
chart into one of 100 available memory
slots.
To retrieve your readings from the

memory, press then (Load) key,
select a memory slot number and press
(OK).
To rename any existing memory slot, press (Functional key)

and (Edit) key combination.
SWR mode
To watch the SWR at a single frequency,
press the (SWR) key.
Do not forget to press the (OK)

key to start or stop the measurement.
Change the frequency with (Left)
or (Right) cursor keys, or press
the (Frequency) key to enter a new
frequency.
The SWR icon in the top-left corner flashes

when the measurement is performed.
10 User’s manual
Display all parameters
To display various parameters of a load
on a single screen, press the (All)
key.
Do not be confused by negative values of L or C. This can be useful for

experienced users.
This screen displays values for series as well as parallel models

of impedance of a load.
• In the series model, impedance is • In the parallel model, impedance is

expressed as resistance and reactance expressed as resistance and reactance
connected in series: connected in parallel:
R
Z = R + jX Z = R ||+ jX R X
X

MultiSWR mode
Press the (Functional key) and
(Multi) key combination to see the SWR
at up to five different frequencies. This
mode may be useful for tuning multi-
band antennas.
Use (Up) and (Down) cursor keys to select a frequency to be set or changed,
then press the (Frequency) key to enter a new value. Do not forget to press the
(OK) key to start the measurement.
12 User’s manual
Applications
Antennas
Checking the antenna
It is a good idea to check an antenna

before connecting it to the receiving or
transmitting equipment. The SWR chart
mode is good for this purpose.
The picture on the left shows the

SWR chart of a car VHF antenna. The
operating frequency is 145.5 MHz. The
SWR at this frequency is about 1.25,
which is acceptable.
The next screen shot shows SWR chart

of another car antenna. The actual
resonant frequency is about 146.7 MHz,
which is too far from the desired one.
The SWR at 145.5 MHz is 2.7, which is
not acceptable in most cases.

Adjusting the antenna
When the measurement diagnoses that the antenna is off the desired frequency, the
analyzer can help in adjusting it. Physical dimensions of a simple antenna (such as a
dipole) can be adjusted knowing the actual resonant frequency and the desired one.
Other types of antennas may contain more than one element to adjust (including coils,
filters, etc.), so this method will not work. Instead, you may use the SWR mode, the
All parameters mode or the Smith chart mode to continuously see the results while
adjusting various parameters of the antenna.
For multi-band antennas, use the MultiSWR mode. You can easily see how changing
one of the adjustment elements (trimming capacitor, coil, or physical length of an
aerial) affects SWR at up to five different frequencies.
Coaxial lines
Open- and short-circuited cables
The pictures on the right show R and
X charts for a piece of cable with
open- and short-circuited far end. A
resonant frequency is a point at which X
(reactance) equals to zero:
• In the open-circuited case, resonant
frequencies correspond to (left
to right) 1/4, 3/4, 5/4, etc. of the
wavelength in this cable;
• For the short-circuited cable, these
points are located at 1/2, 1, 3/2, etc.
of the wavelength.
14 User’s manual
Cable length measurement
Resonant frequencies of a cable depend on its length as well as on the velocity factor.
A velocity factor is a parameter which characterizes the slowdown of the speed of

the wave in the cable compared to vacuum. The speed of wave (or light) in vacuum is
known as the electromagnetic constant: c =299,792,458 meters (or 983,571,056 feet)
per second.
Each type of cable has different velocity factor: for instance, for RG-58 it is 0.66.
Notice that this parameter may vary depending on the manufacturing process and
materials the cable is made of.
To measure the physical length of a cable,
1. Locate a resonant frequency by using the R,X chart.
Example:
The 1/4-wave resonant frequency of a

piece of open-circuited RG-58 cable is
4100 kHz.
2. Knowing the electromagnetic 299,792,458 × 0.66 =

constant and the velocity factor of the 197,863,022 meters per second
particular type of cable, find the speed of
- or -
electromagnetic wave in this cable.
983,571,056 × 0.66 =
649,156,897 feet per second

3. Calculate the physical length of the 197,863,022 / 4,100,000 ×(1/4) =
cable by dividing the above speed by 12.06 meters
the resonant frequency (in Hz) and
- or -
multiplying the result by the number
which corresponds to the location of this 649,156,897 / 4,100,000 ×(1/4) =
resonant frequency (1/4, 1/2, 3/4, 1, 5/4, 39.58 feet
etc.)
Velocity factor measurement

For a known resonant frequency and physical length of a cable, the actual value of the
velocity factor can be easily measured:
1. Locate a resonant frequency as Example:

described above. 5 meters (16.4 feet) of open-circuited
cable. Resonant frequency is 9400 kHz
at the 1/4-wave point.
2. Calculate the speed of electromagnetic 5 / (1/4) × 9,400,000 =

wave in this cable. Divide the length 188,000,000 meters per second
by 1/4, 1/2, 3/4, etc. (depending on the
- or -
location of the resonant frequency), then
multiply by the resonant frequency (in 16.4 / (1/4) × 9,400,000 =
Hz). 616,640,000 feet per second
3. Finally, find the velocity factor. 188,000,000 / 299,792,458 = 0.63

Just divide the above speed by the - or -
electromagnetic constant.
616,640,000 / 983,571,056 = 0.63
16 User’s manual
Cable fault location
To locate the position of a probable fault in a cable, just use the same method as when
measuring its length. Watch the behavior of the reactive component (X) near the zero
frequency:
• If the value of X is moving from –∞ to 0, the cable is open-circuited:
• If the value of X is moving from 0 to +∞ , the cable is short-circuited:

Making 1/4-λ, 1/2-λ and other coaxial stubs
Pieces of cable of certain electrical

Example:
length are often used as components of
baluns (balancing units), transmission 1/4-λ stub for 28.2 MHz, cable is RG-
line transformers or delay lines. To make 58 (velocity factor is 0.66)
a stub of the predetermined electrical
length,
1. Calculate the physical length. Divide 299,792,458 / 28,200,000 × 0.66 ×
the electromagnetic constant by the (1/4) = 1.75 meters
required frequency (in Hz). Multiply the
- or -
result by the velocity factor of the cable,
then multiply by the desired ratio (in 983,571,056 / 28,200,000 × 0.66 ×
respect to λ). (1/4) = 5.75 feet
2. Cut a piece of cable slightly longer than
this value. Connect it to the analyzer. The A piece of 1.85 m (6.07 ft) was cut.
cable must be open-circuited at the far The margin is 10 cm (0.33 ft). The
end for 1/4-λ, 3/4-λ, etc. stubs, and cable is open-circuited at the far end.
short-circuited for 1/2-λ, λ, 3/2-λ, etc.
ones.
3. Switch the analyzer to the All

28,200 kHz was set.
parameters measurement mode. Set the
frequency the stub is designed for.
4. Cut little pieces (1/10 to 1/5 of the

11 cm (0.36 ft) were cut off.
margin) from the far end of the cable
until the X value falls to zero (or changes
its sign). Do not forget to restore the
open-circuit, if needed.
18 User’s manual
Measuring the characteristic impedance
The characteristic impedance is one of the main parameters of any coaxial cable.
Usually, its value is printed on the cable by the manufacturer. However, in certain cases
the exact value of the characteristic impedance is unknown or is in question.
To measure the characteristic impedance of a cable,
1. Connect a non-inductive resistor

Example 1: 50-Ohm cable with 75 Ohm
to the far end of the cable. The exact
resistor at the far end.
value of this resistor is not important.
However, it is recommended to use 50 to Example 2: Unknown cable with 50
100 Ohm resistors. Ohm resistor at the far end.
2. Enter the R,X chart mode and make

measurement in a reasonably large
frequency range (for instance, 0 to 200
MHz).
Example 1: Example 2:
50-Ohm cable Unknown cable

3. Changing the display range and
Example 1:
performing additional scans, find a
30.00 MHz – min., 60.00 MHz – max.
frequency where R (resistance) reaches
its maximum, and another frequency Example 2:
with minimum. At these points, X 41.00 MHz – max., 88.40 MHz – min.
(reactance) will cross the zero line.
4. Switch to the Data at cursor screen Example 1:

by pressing the (Data) key and 33.0 Ohm – min., 78.5 Ohm – max.
find values of R at previously found Example 2:
frequencies. 99.2 Ohm – max, 53.4 Ohm – min.
5. Calculate the square root of the Example 1:

product of these two values. square root of (33.0 × 78.5) =
50.7 Ohm
Example 2:
square root of (99.2 × 53.4) =
72.8 Ohm
The Tools menu (see page 26) contains several automated tools for coaxial line
calculations.
20 User’s manual
Measurement of other elements
Although RigExpert AA-230 ZOOM is designed for use with antennas and antenna-
feeder paths, it may be successfully used to measure parameters of other RF elements.
Capacitors and inductors

The analyzer can measure capacitance from a few pF to about 0.1 μF as well as
inductance from a few nH to about 100 μH. Since measuring of capacitance and
inductance is not a main purpose of RigExpert analyzers, the user will have to gain
some experience in such measurements.
Be sure to place the capacitor or the inductor as close as possible to the RF connector
of the analyzer.
1. Enter the R,X chart mode and select a reasonably large scanning range. Perform a
scan.
Unknown capacitor Unknown inductor

2. By using left and right arrow keys, scroll to the frequency where X is -25…-100 Ohm
for capacitors or 25…100 Ohm for inductors. Change the scanning range and perform
additional scans, if needed.
3. Switch to the Data at cursor screen by pressing the key and read the value of
capacitance or inductance.
Unknown capacitor Unknown inductor
Transformers
RigExpert analyzers can also be used for checking RF transformers. Connect a 50 Ohm
resistor to the secondary coil (for 1:1 transformers) and use SWR chart, R,X chart or
Smith chart modes to check the frequency response of the transformer. Similarly, use
resistors with other values for non-1:1 transformers.
22 User’s manual
Traps
A trap is usually a resonant L-C network used in multi-band antennas. By using a
simple one-turn wire coil, a resonant frequency of a trap may be measured.
Example:
A coaxial trap constructed of 5 turns
of TV cable (coil diameter is 6 cm) was
measured.
A one-turn coil (about 10 cm in

diameter) connected to the analyzer
was placed, co-axially, a few
centimeters away from the measured
trap. The SWR chart shows a visible
dip near 17.4 MHz, which is a resonant
frequency of the trap.

Annex 1 Optional open-short-load calibration.
Specifications RF output:
• Connector type: N
• Output signal shape: square
• Output power: -10 dBm (at 50 Ohm
Frequency range: 0.1 to 230 MHz load)
Frequency entry: 1 kHz resolution Power:
Measurement for 25, 50, 75, 100, 150, • Four 1.5V alkaline batteries, type AAA
200, 300, 450, and • Four 1.2V Ni-MH batteries, type AAA
600-Ohm systems • Max. 4 hours of continuous
measurement, max. 2 days in stand-
SWR measurement range:
by mode when fully charged batteries
• 1 to 100 in numerical modes
are used
• 1 to 10 in chart modes
• When the analyzer is connected to a
SWR display: numerical or analog PC or a DC adapter with USB socket, it
indicator takes power from these sources
R and X range: Interface:
• 0…10000, -10000…10000 Ohm • 290×220 color TFT display
in numerical modes • 6x3 keys on the water-proof keypad
• 0…1000, -1000…1000 Ohm in chart • Multilingual menus and help screens
modes • USB connection to a personal
Display modes: computer
• SWR at single or multiple frequencies AA-230 ZOOM Option BLE:
• SWR, return loss, R, X, Z, L, C Bluetooth Specification v.4.2, LE
at single frequency
• SWR chart, 20 to 500 points Dimensions: 82 × 182 × 32 mm
• R, X chart, 20 to 500 points (3.2 × 7.2 × 1.3 in)
• Smith chart, 20 to 500 points Operating temperature: 0…40 °C
• Return loss chart, 20 to 500 points (32…104 °F)
• TDR chart (Time Domain Weight: 236 g (8.32 oz)
Reflectometer)
Warranty: 2 years
• Cable tools (stub tuner, length
& velocity factor, cable loss
Made in Ukraine.
and characteristic impedance
measurement)
24 User’s manual
Annex 2
Precautions
Never connect the analyzer to your antenna in thunderstorms.

Lightning strikes as well as static discharge may kill the operator.
Never leave the analyzer connected to your antenna after you fin-
ished operating it. Occasional lightning strikes or nearby trans-
mitters may permanently damage it.
Never inject RF signal or DC voltage into the antenna connector of

the analyzer. Do not connect it to your antenna if you have active
transmitters nearby.
Avoid static discharge while connecting a cable to the analyzer. It

is recommended to ground the cable before connecting it.
Do not leave the analyzer in active measurement mode when you

are not actually using it. This may cause interference to nearby
receivers.
If using a personal computer, first connect the cable to the antenna

connector of the analyzer, then plug the analyzer to the computer
USB port. This will protect the analyzer from static discharges.

Annex 3
Tools menu
For the quick access to the the Tools menu, press the + key combination.
Stub tuner
The Stub tuner mode is designed to
help making or checking 1/4-λ or 1/2-λ
coaxial stubs.
Connect either open or short circuited

cable to the analyzer and press
(OK) to start.
The analyzer will immediately show

resonant frequencies for both
quarterwave and halfwave stubs.
Longer cables have lower resonant

frequency.
26 User’s manual
Length & VF
Knowing the velocity factor, a physical
length of a cable can be easily calculated.
Press the (Up) button and edit the
value of the velocity factor, then press
(OK) to start measurement.
To find the velocity factor of an unknown

cable, press the (Down) key and
enter the physical length, then press
(OK).
The velocity factor depends on a type of your transmission line.

For instance, RG-58 cable with polyethylene insulator has VF=0.66.

Cable loss
To measure the loss in a coaxial cable,
connect a piece of a cable to the antenna
connector of the analyzer. Make sure
the far end of the cable is open circuited.
Press (OK) to start.
Next, short circuit the far end of the cable

and press (OK) to continue.
Once the analyzer finishes the

measurement, you will see the Loss
versus frequency chart. Use (Left)
and (Right) cursor keys to change
frequency and watch the loss value in
decibels at the bottom of the analyzer’s
screen.
To see the list of other keypad shortcuts,

press the (Help) key.
28 User’s manual
Cable impedance
To measure the characteristic
impedance, use a piece of an open
circuited cable: a half of a meter (or a
foot) or longer should be fine. Press
(OK) to start.
Next, the far end of the cable should

be short circuited. Press (OK) to
continue.
There are several reasons why the

resulting chart does not look smooth,
so we need to use (Left) and
(Right) cursor keys to find the location
where the impedance is stable. The
result is shown at the bottom left corner
of the screen.
Use + (Up) and +

(Down) key combinations to change the
scale, if needed.

Self tests
There are several built-in self tests in the
AA-230 ZOOM analyzer, which can be
run by the user to make sure the analyzer
is working properly.
Make sure all cables or adapters

are disconnected from the antenna
connector of your analyzer, then press
(OK) to start the first test (Detector
test).
You should see the “Passed” message in

case of success.
Continue with two more tests: the second

(Built-in filter test) and the third (Test
with load). For the third test, make sure
to connect a good 50 Ohm load directly
to the analyzer’s antenna connector. See
page 38 to know more about 50 Ohm
loads.
30 User’s manual
Annex 4
Setup menu
For the quick access to the Setup menu,

press the + key combination.
There are several settings in the Setup

menu:
• Language – select a language for the
analyzer’s menus
• Palette – choose a color scheme
• Battery – select a power consumption
scheme
• Sound – select sound volume
• Sys. imp. – select system impedance
(25, 50, 75 or 100 Ohm) which affects
SWR and return loss readings.
• Units – select metric (meters) or
imperial (feet) units
• Bands – select region for highlighting
of radio amateur bands
• Cable vel. factor – choose a velocity
factor of the coaxial cable for the TDR
mode
• Freq. corr. – frequency correction of
the analyzer’s oscillator
• Data points – select a number of data
points for each frequency sweep
• Reset settings – reset the analyzer to
factory defaults
• Clear saved charts – clear all memory
slots

Annex 5
TDR mode
Theory
Time domain reflectometers (TDR) are electronic instruments used for locating faults
in transmission lines.
A short electrical pulse is sent over

the line, and then a reflected pulse is
observed. By knowing the delay between
two pulses, the speed of light and the
cable velocity factor, the DTF (distance-
to-fault) is calculated. The amplitude and
the shape of the reflected pulse give the
operator idea about the nature of the
fault.
Instead of a short pulse, a “step” function

may be sent over the cable.
32 User’s manual
Unlike many other commercially-available reflectometers, RigExpert AA-230 ZOOM
does not send pulses into the cable. Instead, another technique is used. First, R and
X (the real and the imaginary part of the impedance) are measured over the whole
frequency range (up to 230 MHz). Then, the IFFT (Inverse Fast Fourier Transform) is
applied to the data. As a result, impulse response and step response are calculated.
This method is often called a “Frequency Domain Reflectometry ”, but the “ TDR” term
is used in this document since all calculations are made internally and the user can
only see the final result.
The vertical axis of the resulting chart displays the reflection coefficient: Γ=-1 for short
load, 0 for matched impedance load (ZLoad=Z0), or +1 for open load. By knowing the
cable velocity factor, the horizontal axis is shown in the units of length.
Single or multiple discontinuities can be displayed on these charts. While the Impulse
Response chart is suitable for measuring distance, the Step Response chart helps in
finding the cause of a fault.
See the examples of typical Step Response charts on the next page.

34 User’s manual
Practice
Press + (TDR) to open Impulse Response (IR) and Step Response (SR)
charts:
The velocity factor of the cable, as well as display units (meters or feet) may be
changed in the Settings menu. You may disconnect your antenna or leave it connected
to the far end of the cable. This will only affect the part of the chart located behind the
far end of the cable.
The (OK) key starts a new measurement, which will take some time. Use the arrow
keys to move the cursor or to change the display range. Watch the navigation bar at
the top-right corner of the screen to see the current position of the displayed part of
the chart.
The (Save) key will start a new measurement, saving results in one of 100 memory
slots. The key will retrieve saved data. Use the + combination to edit
memory names, if needed. Pressing (Data) opens a data screen which displays
numerical values of impulse and step response coefficients, as well as Z (estimated
impedance) at cursor. The key will display the help screen, as usual.

Annex 6
Calibration
Although RigExpert AA-230 ZOOM is designed for high performance without any
calibration, an open-short-load calibration may be applied for better precision.
The standards used for calibration should be of high quality. This requirement is
especially important for high frequencies (100 MHz and upper). Three different
calibration standards should be used: an “open”, a “short” and a “load” (usually, a
50-Ohm resistor). A place where these standards are connected during calibration is
called a reference plane. If the calibration is done at the far end of a transmission line,
parameters of this line will be subtracted from measurement results and the analyzer
will display “true” parameters of a load.
36 User’s manual
To perform an open-short-load
calibration, select Calibrate in the Main
menu (or just press the + key
combination).
Following the instructions on the screen,

connect “open“, “short“ and “load“
calibration standards to the antenna
connector of the analyzer.
You may connect calibration standards

to the far end of a cable, so the cable
will be “nulled”.
To apply calibration, press the

+ key combination in any
measurement mode. The “CAL“ mark will
appear at the bottom left corner of the
screen.

Annex 7
Dummy loads Amphenol
202109-10
1 Watt
terminator plug
Low SWR
50 Ohm dummy loads are not all equal.
For calibration (see page 32), please use

low-power RF terminators which provide
low SWR over the wide frequency range.
High-power terminators, especially

connected via long cables, are suitable
neither for calibration purposes (page
32), nor for analyzer self-tests (page 30).
Bird 8201
500 Watt oil-cooled termination
High SWR
38 User’s manual
EC DECLARATION OF CONFORMITY
In accordance with EN ISO 17050-1: 2004
We, Rig Expert Ukraine Ltd. of 2 Solomenska Ploscha, Kyiv, 03035, Ukraine
Declare under our sole responsibility that the product:
Equipment Antenna and cable analyser
Brand name RigExpert
Model number AA-230 ZOOM
to which this declaration relates, is in conformity with the following standards and / or
other normative documents:
Reference No.: Title: Edition / Date:
IEC 61000-4-2 Testing and measurement techniques - 2009

Electrostatic discharge immunity test
IEC 61000-4-3 Testing and measurement techniques - 2006
Radiated, radio-frequency,
electromagnetic field immunity test
We hereby declare that the above named product is in conformity to all the applicable
essential requirements of directive 2004/108/EC (the EMC Directive).
The technical documentation relevant to the above equipment will be held at:
SEDAM Communications Limited

Old Mill Cottage, Shillington Rd, Gravenhurst, MK45 4JE, The United Kingdom
/Denys Nechytailov/ December 1, 2018

Director

For private households: Information on Disposal for Users of WEEE
This symbol on the product(s) and / or accompanying documents means
that used electrical and electronic equipment (WEEE) should not be mixed
with general household waste. For proper treatment, recovery and recycling,
please take this product(s) to designated collection points where it will be
accepted free of charge.
Alternatively, in some countries, you may be able to return your products to your local retailer upon
purchase of an equivalent new product. Disposing of this product correctly will help save valuable
resources and prevent any potential negative effects on human health and the environment, which
could otherwise arise from inappropriate waste handling.
Please contact your local authority for further details of your nearest designated collection point.
Penalties may be applicable for incorrect disposal of this waste, in accordance with your national
legislation.
For professional users in the European Union
If you wish to discard electrical and electronic equipment (EEE), please contact your dealer or
supplier for further information.
For disposal in countries outside of the European Union
This symbol is only valid in the European Union (EU). If you wish to discard this product,
please contact your local authorities or dealer and ask for the correct method of disposal.
http://www.rigexpert.com
Copyright © 2015-2018 Rig Expert Ukraine Ltd.
“RigExpert” is a registered trademark of Rig Expert Ukraine Ltd.
Doc. date: 07-Dec-2018

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Forţa lui Lorentz pentru o particulă încărcată electric cu sarcina q care se

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θJA2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C/W OFSA 3 AD8302 12 MSET

VPOS 4 TOP VIEW 11 VREF

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C INPB 6 9 VPHS

PIN FUNCTION DESCRIPTIONS

4k⍀ + 750⍀ 25⍀

COMM COMM COMM

Circuit C Circuit D Circuit E

0.8 0.75 +85ⴗC –0.5

2.0 1.80 3.0

1.80 3.0 1.80 3.0

1.20 1.0 1.20 1.0

0.45 –1.5 0.45 –1.5

0.30 –2.0 0.30 –2.0

0.15 –2.5 0.15 –2.5

3.0 1.8 3.0

0.5 –15dBm 0.5

–1.5 +25 C –1.5

–3.0 0.0 –3.0

–40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90

200mV PER 0.08

100MHz 900MHz 1.62 8

0.0 0.00 –10

0.00 –10 0.00 –10

0.00 –10 –10

6 0.05 MEAN +3 SIGMA

CHANGE IN VPHS SLOPE – mV

–2 –0.15 MEAN –3 SIGMA

2␮s HORIZONTAL 0.18

PINPA = –45dBm 1.26

3000 REAL SHUNT Z (⍀) 3.0

TPC 50. VREF Output Noise Spectral Density vs.

distinguish between ±90°, it is considered to have an unambiguous R4

VMAG = (RF ISLP / 20) (PINA − PINB ) + VCP

Figure 3. Simplified Block Diagram of the Output Interface 900mV VCP

MAX RANGE FOR VREF = VREFOPT

relative phase is held constant while the magnitude difference is MSET

modulated, i.e., an expected magnitude response and a residual

1.8 V if Phase > PhaseSP

Figure 8. Increasing the Slope Requires the Inclusion of a C7

Figure 10. Disconnecting the Feedback to the Setpoint