Curs 1

A.E.T.
S.l. dr. ing. Ionel Petrescu
 Structura cursului

• Notiuni de automatizari

•Structura FPGA

• Schematics

• Simularea circuitelor

• Limbajul VHDL
09:17 2
 Notare

Laborator: 40%
Examen: 60%
•Examen partial: 30%
•Examen final: 30%

09:17 3
 Obiectivele cursului
Acumularea de cunostinte si abilitati privind:

– Automatizarea proceselor
– Bucle de reglare
– Programarea cu limbajul de descriere hardware
VHDL
– Sinteza si simularea circuitelor electronice digitale
sau sistemelor care pot fi implementate fizic.
– Implementarea programelor scrise in limbajul VHDL,
pe structura reprogramabila FPGA

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 Cunostinte minime necesare pentru promovarea
examenului

• Sinteza si simularea circuitelor

electronice digitale elementare

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 Referinte bibliografice
1. D. Burdia, G.S. Popescu, Proiectare asistata de calculator a circuitelor
electronice, MATRIXROM, 1999
2. G. Toacse, D. Nicula, Electronica Digitala, Teora, 1996
3. G.V. Iana, G. Şerban, L. Ionescu, P. Anghelescu, PROGRAMAREA CU LIMBAJE
DE DESCRIERE HARDWARE, UNIVERSITATEA DIN PITESTI, 2009
4. S. Brown, Z. Vranesic, Fundamentals of Digital Logic With VHDL
Design, University of Toronto, McGraw Hill, 2005
5. D. L. Perry, VHDL Programming by Examle, McGraw Hill, 2002
3. J. Weber, M. Meaudre, Le langage VHDL Cours et exercises, Dumond,
2004
6. IEEE Computer Society, 1076 IEEE Standard VHDL – Language
Reference Manual, IEEE, 2002
7. V. A. Pedroni, Circuit Design with VHDL, Cambrige, MIT Press, 2004
8. P.P.Chu, FPGA Prototyping by VHDL Examples – Xilinx Spartan 3
Version, WILEY, 2008
9. www.xilinx.com
10. www.digilentinc.com
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 Glosar
CAD - Computer Aided Drafting , Computer Aided Design
ECAD - Electronic Computer Aided Design
CAE - Computer Aided Engineering
VHDL - VHSIC Hardware Description Language
VHSIC - Very High Speed Integrated Circuits
CPLD - Complex Programmable Logic Devices
FPGA - Field Programmable Gate Arrays
ASIC - Application Specific Integrated Circuits
RTL – Register-Transfer Level
HDL - Hardware Description Language
DSP - Digital Signal Processor
GPP - General Purpose Processor
RISC - Reduced Instruction Set Computer

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• Automatizare – efectuarea repetitiva a unor
operatii fara interventia umana directa
• Procesele automatizate necesita
senzori/traductoare si/sau actuatori.

• Sistemele automatizate necesita bucle de

reglare (reactie negativa)
• Regulatoarele cu reactie negativa fac un sistem
continuu sa fie stabil
• In timpul functionarii se folosesc puncte de reglaj
• Pentru descrierea regulatoarelor se folosesc
scheme bloc
• Schemele bloc se convertesc in ecuatii matematice
pentru analiza sistemului
• Sistemele cu functionare continua folosesc
controlere P, PI, PD, PID
 Control (reactia)
• Liniar (proportional)
• PID (PI, PD)
• Fuzzy
• RN
PID
• Termenul proportional, Kp, mentine sistemul
pe directia dorita.
• Termenul derivativ, Kd, raspunde rapid la
schimbari.
• Termenul integral, Ki, raspunde la erorile pe
termen lung.
 Sistem Fuzzy
• Sistemul Fuzzy foloseste, pentru control, reguli
ce pot fi exprimate verbal si seturi de functii
membre,
• Este utilizat pentru sistemele ce nu pot fi
modelate cu ecuatii diferentiale.
• 1. If (bucket is full) then (stop filling)
2. If (bucket is half full) then (fill slowly)
3. If (bucket is empty) then (fill quickly
1. If verror is LP and
d/dtverror is any then
Vmotor is LP.

2. If verror is SP and
d/dtverror is SP or ZE
then Vmotor is SP.

3. If verror is ZE and
d/dtverror is SP then
Vmotor is ZE.

4. If verror is ZE and
d/dtverror is SN then
Vmotor is SN.

5. If verror is SN and
d/dtverror is SN then
Vmotor is SN.

6. If verror is LN and
d/dtverror is any then
Vmotor is LN.
 Exemplu
• Consider the case where verror = 30 rps and
d/dt verror = 1 rps/s.
Functii membre - exemplu
RN
Functia de activare
 Implementari
• Relee (digitale)
• Optocuploare (digitale)
• uC/uP
• PLC
• PLD
Proiectare
 Curs AET 2

Introducere

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 – În proiectele electronice de inceput erau folosite componente
analogice care au un preţ relativ redus, însă, dezavantajele
principale ale sistemelor analogice constau în:
– sensibilitate la variaţiile de temperatură,
– îmbătrânirea mai rapidă a componentelor,
– dificultatea de a îmbunătăţi sistemul cu noi caracteristici.
– Sistemele digitale elimină abaterile cauzate de variaţiile de
temperatură, iar îmbunătăţirea caracteristicilor sistemului la un
moment dat se poate realiza foarte uşor prin modificarea
softului procesorului programabil conţinut de sistem.

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Principalele circuite digitale complexe sunt:

- Procesoare digitale de semnal (DSP)

- Microcontrolerele (MCU)
- Microprocesoare de uz general /
microprocesoare cu set redus de
instrucţiuni (GPP/RISC )
- Arii de porţi logice programabile (FPGA )
- Circuite integrate dedicate (ASIC)
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 Comparaţie între cele cinci arhitecturi de circuite
digitale ţinându-se cont de câteva criterii:

• timp de lansare pe piaţă - primă importanţă

• performanţa - primă importanţă
• preţ - primă importanţă
• facilităţi de dezvoltare - primă importanţă
• consum de putere - importanţă medie
• flexibilitate ulterioară - importanţă redusă

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 Uşurinţă
Implementare Consum de Flexibilitate Concluzii
Performanţa Preţ în
pe piaţă putere ulterioară
dezvoltare

ASIC Nesatisfăcător Foarte Bun Foarte Bun Satisfăcător Bun Nesatisfăcător Satisfăcător

Foarte
DSP Foarte Bun Bun Bun Foarte Bun Foarte Bun Foarte Bun
Bun

Foarte
FPGA Bun Foarte Bun Bunr Satisfăcător Bun Bun
Bun

MCU Foarte Bun Satisfăcător Foarte Bun Bun Satisfăcător Foarte Bun Bun

RISC/
Bun Bun Satisfăcător Bun Satisfăcător Foarte Bun Bun
GPP

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 INTRODUCERE ÎN DOMENIUL CIRCUITELOR LOGICE
PROGRAMABILE

• PLD (Programmable Logic Devices) -

circuit integrat care poate fi configurat de
către utilizator pentru implementarea unui
proiect.

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 ROM

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 ROM
• Constituit dintr-o arie de dispozitive
semiconductoare interconectate astfel incat sa
stocheze o matrice de date binare.
• O ROM cu n intrari si m iesiri contine o matrice
de 2n cuvinte de m biti lungime.
• Poate stoca orice tip de circuit combinational.
• Look-up table - stocheaza toate combinatiile
de intrari

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 Exemplu look-up table

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 Tipuri de ROM
• Mask programmable ROM
• User programmable ROM (PROM)
• EPROM
• EEPROM
• FLASH

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• Unul dintre cele mai folosite circuite logice
programabile a fost memoria de tip ROM
programabilă o singură dată (PROM).

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PROM neprogramat
PROM programat
• Plecând de la această arhitectură s-au
dezvoltat ariile logice programabile de tip PLA
(Programmable Logic Array) dedicate
implementării funcţiilor logice.
• Combinarea structurii PLA-urilor cu
tehnologia PROM a avut ca rezultat
dezvoltarea dispozitivelor logice programabile
de tip FPLA (Field Programmable Logic
Array), care au apărut pe piaţă la mijlocul
anilor ’70.
 Dispozitive logice programabile
simple
• În general circuitele PLD cu densitate
redusă de porţi logice (PLA şi PAL), sunt
prezente pe piaţă în capsule de 20 sau 44
de pini şi au o densitate cuprinsă între 100
şi 999 porţi logice.
• Se mai numesc circuite logice programabile
simple sau SPLD-uri (Simple PLD).
• Structura de tip arie logică SI-SAU
recomandă folosirea circuitele SPLD pentru
implementarea ecuaţiilor logice sub forma
sumelor de produse.
• Unele dintre îmbunătăţirile recente ale
circuitelor SPLD sunt:
– porturi de intrare/ieşire programabile,
– porturi de intrare/ieşire bidirecţionale,
– registre de configurare mai flexibile şi
– o schemă de clock mai flexibilă.
• Circuitele SPLD sunt mai uşor de utilizat, de
proiectat şi programat.
• Produsele care beneficiază de avantajele oferite
de circuitele SPLD sunt componentele de reţea
care cer performanţe ridicate per ansamblu:
– hub-uri de reţea
– bridge-uri,
– routere.
• Alte produse vizate de SPLD-uri sunt: sunt cele
din zona telefoniei mobile, video game-urilor şi a
hand-held web browserelor.
 Programmable Logic Arrays
• m functii cu n variabile

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 PLA

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 PLA

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• FPLA-urile au un număr fix de intrări, de ieşiri
şi un număr fix de termeni de tipul produs.
• Avantajul oferit de circuitele din această
familie este că atât aria logică de porţi ŞI cât
şi cea de porţi SAU sunt programabile
• Totuşi acest tip de circuite logice
programabile au avut un succes limitat
deoarece aveau viteză scăzută de lucru şi
erau dificil de programat.
• Logica programată a devenit mai populară la
mijlocul anilor 1970 odată cu apariţia ariilor
logice programabile de tip PAL-uri
(Programmable Array Logic).
• Acest tip de arhitectură combină o arie
programabilă de porţi ŞI cu o arie de porţi
SAU fixă (spre deosebire de circuitele PLA la
care atât aria de porţi ŞI cât şi cea de porţi
SAU sunt programabile).
 Programmable Array Logic

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 Programmable Logic Devices/Generic
Array Logic

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 Complex Programmable Logic Devices

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 CPLD

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 Programming Technologies
• Fuse and anti-fuse - OTP
– fuse makes or breaks link between two wires
– typical connections are 50-300 ohm
– one-time programmable
• Flash/EEPROM
– High density
– Process issues
• RAM-based - volatile
– memory bit controls a switch that
connects/disconnects two wires
– typical connections are .5K-1K ohm
– can be programmed and re-programmed easily
(tested at factory)
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simple programmable function
 Fusible link
technologies
 Antifuse
technologies
OTP
Mask-programmed device
PROMs
EPROM-based technologies
An EPROM transistor-based memory
cell.
EEPROM-based technologies
 FLASH-based technologies
• Similar cu EPROM sau EEPROM, dar cu strat
mai subtire de oxid
Curs 3

FPGA
Technology timeline (dates are
approximate)
Arhitecturi
 FPGA Programming Technologies
• Static RAM programming technology
• EPROM/EEPROM/Flash programming
technology
• Antifuse programming technology
SRAM Programming Technology
Programmable Logic Block
Architectures
CLB

9
Look-Up Table–Based Programmable
Logic Blocks
CLB – LUT based

12
LUT - based

13
Logic Blocks Based on Multiplexers and
Gates
MUX - based

16
XILINX Logic Cell

17
Programmable Interconnects
Interconnects in Symmetric Array FPGAs
General-Purpose Interconnect
Interconnects in Symmetric Array FPGAs
Direct Interconnects
Interconnects in Symmetric Array FPGAs
Global Lines
Interconnects in Row-Based FPGAs
Programmable I/O Blocks in FPGAs
 Dedicated Specialized Components in
FPGAs
• Dedicated Memory
• Dedicated Arithmetic Units
• Digital Signal Processing Blocks
• Embedded Processors
• Content Addressable Memories
Other Blocks

26
Other Blocks – MAC (multiplier and
adder cell)

27
Other Blocks - Clock managers

28
 Other Blocks - Clock managers
• Jitter removal
• Frequency synthesis
• Phase shifting
• Clock multiplication
• Clock division

29
Other Blocks

30
 Xilinx FPGA
• Xilinx refers to the “interconnection switches” as the
switch matrix
IOB IOB IOB IOB

IOB

IOB
CLB CLB CLB CLB

SM SM SM
Programmable
Switch Matrix
IOB

IOB
CLB CLB CLB CLB

SM SM SM
IOB

IOB
CLB CLB CLB CLB

SM SM SM
IOB

IOB
CLB CLB CLB CLB

IOB IOB IOB IOB 31

 FPGAs
• Programmable Switch Matrix

programmable switch element

turning the corner, etc.

32
 FPGAs
• An example of programming an FPGA
x3 f

f1  x1 x2
x1 f 2  x2 x3
x1 0 x2 0
0 1 f  x1 x2  x2 x3
f1 f2
0 0
x2 1 x3 0
x2

f1 0
1 x1
f3
1 0/1
f2 1 0/1 f
LUT 0/1
0/1
x2

33
 FPGAs
• An example of programming an FPGA
x3 f

f1  x1 x2
x1 f 2  x2 x3
x1 0 x2 0
0 1 f  x1 x2  x2 x3
f1 f2
0 0
x2 1 x3 0
x2

f1 0
1 x1
f3
1 0/1
f2 1 0/1 f
LUT 0/1
0/1
x2

34
 Configuration Storage Elements
• Static Random Access Memory (SRAM)
– Logical configuration is controlled by the state of
SRAM bits
– FPGA needs to be configured at power-on by another
separated ROM
• Flash Erasable Programmable ROM (Flash)
– Logical configuration is implemented by floating-gate
transistors that can be turned off by injecting charge
onto its gate.
– FPGA itself holds the program
– reprogrammable, even in-circuit

35
36
 Curs 4

INTRODUCERE ÎN LIMBAJUL DE
DESCRIERE
HARDWARE – VHDL
• VHDL -> VHSIC Hardware Description
Language (limbajul de descriere hard
VHSIC)
• VHSIC -> Very High Speed Integrated
Circuit.
• set de unelte pentru sinteză (synthesis
tools).
• creeaza structuri de circuite logice direct
din descrierile VHDL comportamentale.
• pot fi proiectate, simulate şi sintetizate atât
circuitele combinaţionale simple cât şi
sisteme complexe cu microprocesor
Design
flow
 Modalităţi de proiectare cu circuite
PLD
• Metoda de bază în proiectarea cu circuite
logice programabile cuprinde trei faze:
- descrierea proiectului;
- implementarea proiectului;
- verificarea proiectului.
• Mediul software de proiectare XILINX ISE (Integrated Software
Environment) este utilizat la realizarea şi implementarea completă a
unui proiect pentru structurile programabile de tip XILINX.
Componenta software ISE Project Navigator facilitează crearea
proiectului, organizându-l pe următoarele etape:
– Descriere proiect. Programatorul are posibilitatea să descrie proiectul prin
introducerea de coduri sursă HDL (Hardware Description Language)
pentru limbajele VHDL, Verilog, Abel sau utilizând schematice şi
diagrame cu stări finite;
– Sinteza. În cadrul acestei etape fişierele de tip VHDL, Verilog sau
schematice sunt transformate în fişiere de tip netlist care sunt acceptate
ca fişiere de intrare la etapa de implementare;
– Implementarea. După sinteză, la implementare, proiectul este adaptat şi
transformat din forma logică digitală în forma tehnologică implementabilă
pe structura reconfigurabilă aleasă;
– Verificarea. Poate fi realizată în toate etapele de implementare ale
proiectului. Utilizarea componentelor software de simulare conduce la
verificarea completă a funcţionalităţii proiectului sau a unor porţiuni de
proiect. De asemenea, pot fi realizate şi verificări directe pe circuit, după
programarea acestuia;
– Configurarea. După generarea fişierelor de programare (bitstream file)
proiectantul are posibilitatea programării circuitului reconfigurabil. În
timpul procesului de configurare sunt programate interconexiunile
structurii FPGA alese.
 Structura unui cod VHDL
• VHDL este un program program structurat, împrumutându-se unele
idei de la limbajele de programare soft Pascal şi Ada.
• O idee de bază este acea de a defini o interfaţă a modulului hard în
timp ce detaliile interne sunt ascunse.
• Astfel o entitate (entity) VHDL este o simplă declarare a intrărilor şi
ieşirilor modulului în timp ce arhitectura (architecture) VHDL este o
descriere structurală sau comportamentală
detailată a funcţionării modulului.
• Acest concept formează bazele proiectării ierarhice a sistemelor, şi
anume arhitectura entităţii de la nivelul cel mai de sus poate conţine
(instantiate) alte entităţi ale căror arhitecturi sunt “invizibile” de la
nivelurile superioare.
• O arhitectură de la nivel superior poate folosii entităţi de la nivelul
inferior de mai multe ori, iar mai multe arhitecturi de la nivel superior
pot folosii aceeaşi entitate de la nivel inferior fiecare la rândul ei.
Conceptul entitate-arhitectură
Conceptul de ierarhie
 Entity – descrie interfata cu lumea
exterioara
entity nume_entitate is
generic(nume generice : type := valori_initiale);
port(nume_porturi : mode tip port);
end entity nume_entitate;

A se observa că după ultimul semnal definit nu se

mai pune punct şi virgulă.
• Pe lângă cuvintele cheie în codul VHDL mai apar următoarele
elemente:
• entity-name = un nume selectat de utilizator pentru a denumi
entitatea;
• port = o listă de unul sau mai mulţi identificatori selectaţi de
utilizator, separaţi prin virgulă care denumesc semnalele externe;
• mode = unul din următoarele patru cuvinte rezervate, specificând
direcţia semnalului:
– in – pentru semnal de intrare în entitate;
– out – pentru semnal de ieşire din entitate, cu menţiunea că,
valoarea semnalului nu poate fi “citită” înăuntrul entităţii, ci numai
de alte entităţi care-l folosesc;
– buffer – defineşte un semnal de ieşire din entitate, iar valoare lui
poate fi citită şi în interiorul arhitecturii din entitate;
– inout – defineşte un semnal de intrare/ieşire din entitate, acest
se foloseşte frecvent pentru a descrie pini three-state.
 Entity
• Porturile declarate într-o entitate sunt vizibile
în toate arhitecturile atribuite acesteia.
• Porturile pot fi de intrare, ieşire, buffer sau
bidirecţionale (IN, OUT, BUFFER, INOUT)
Entity
 Entity - Ports
port (
...list of port declarations...
);

port (
in1, in2 : in bit;
out1 : out bit
);
 Entity - Generics
generic (
...list of generic declarations...
);

generic (
gain : integer := 4;
time_delay : time := 10 ns
);
 Entity - Constants
• constant : rpullup : real := 1000.0;
• constant a : integer := 1;
constant b : real := 0.123;
constant c : std_logic := ‘0’;
 Entity - Exemplu
entity test is
generic (
gain : integer := 4;
time_delay : time := 10 ns
);

port (in1, in2 : in bit;

out1 : out bit
);

constant : rpullup : real := 1000.0;

end entity test;

 Architecture
• Arhitectura descrie relaţia dintre intrările şi
ieşirile porturilor entităţii căreia îi este asociată.
• O arhitectură poate avea asociată doar o
singură entitate, dar o entitate poate avea
asociate mai multe arhitecturi prin configuraţie.
• Descrierea poate fi:
– Behavioral (comportamentala)
– Structural (top)
– Data flow (RTL)
 Structural
• Structural VHDL sau structural coding este un
stil low-level.
• Instantiere, port map.
• Este utilizat de obicei in fiseierele top level.
 RTL
• RTL (Register Transfer Level) se refera la modul
cum sunt conectate semnalele intre registrii
hard si operatiile logice.
 Behavioral
• Urmatorul nivel de abstractizare.
• Utilizeaza structuri de tip ‘‘for loops’’, ‘‘if
statements’’, and ‘‘case statements’’.
architecture nume_arhitectură of nume_entitate is
-- declaraţii în arhitectură

Begin
--specificaţii_concurente

end [ architecture ] [ nume_arhitectură ];

• Zona declarativă a unei arhitecturi poate
conţine declaraţii de tipuri, semnale,
constante, subprograme, componente şi
grupuri.
• Specificaţiile concurente din corpul
arhitecturii definesc legăturile dintre
intrările şi ieşirile modulului digital pe
care-l reprezintă
Sintaxa generala a unui program VHDL
--Declararea librariilor prin clauza library si use
library nume_librarie;
use nume_librarie.nume_pachet.all;
--Declararea entitatii modulului digital
entity nume_entitate is
generic(nume generice : type := valori_initiale);
port(nume_porturi : directie tip port);
end entity nume_entitate; --entity[93]
--Corpul arhitecturii
architecture nume_arhitectura of nume_entitate is
declaratii arhitectura
begin
specificatii concurente
end architecture nume_arhitectura;
 Exemplu
entity And2 is
port (x, y : in BIT;
z: out BIT);
end entity And2;

architecture ex1 of And2 is

begin
z <= x and y after 5ns;
end architecture ex1;
exemplu
 Exemplu entitate
ENTITY exemplu IS
PORT (a, b, c : IN BIT;
y : OUT BIT
);
END exemplu;
 Arhitectura comportamentala
ARHITECTURE ex_comp OF exemplu IS
BEGIN
y <= (a AND b) OR c;
END ex_comp;
 Arhitectura structurala
ENTITY exemplu IS ENTITY and_gate IS
PORT (a, b, c : IN BIT;
PORT (a1, a2 : IN BIT;
y : OUT BIT
); a3 : OUT BIT);
END exemplu; END and_gate;

ARHITECTURE ex_struct OF exemplu IS

COMPONENT and_gate ARHITECTURE and_gate OF and_gate IS
PORT (a1, a2 : IN BIT; BEGIN
a3 : OUT BIT); a3 <= a1 AND a2;
END COMPONENT;
END and_gate;
COMPONENT or_gate
PORT (b1, b2 : IN BIT; ENTITY or_gate IS
b3: OUT BIT); PORT (b1, b2 : IN BIT;
END COMPONENT;
b3 : OUT BIT);
SIGNAL d: BIT; END or_gate;

BEGIN
ARHITECTURE or_gate OF or_gate IS
g1 : and_gate PORT MAP (a, b, d);
g2 : or_gate PORT MAP (c, d, y); BEGIN
END ex_struct; b3 <= b1 OR b2;
END or_gate;
 Curs 5

Limbajul VHDL
 Variables
• variable var1 : integer := 0;
variable var2 : integer := 1;
var1 := var2;
 Signals
• În cadrul unei arhitecturii se pot definii unul sau mai multe semnale
interne, iar acestea în cadrul unei diagrame logice au corespondent
traseele.
SIGNAL signal_name : signal_type [:= initial_value];

• Semnalele pot fi atât scrise cât şi citite în cadrul arhitecturii.

signal sig1 : integer := 0;

signal sig2 : integer := 1;
sig1 <= 14;
sig1 <= sig2;
sig1 <= sig2 after 10 ns;
• Toate semnalele, variabilele şi constantele
dintr-un program VHDL trebuie să aibă
asociat un tip (type).
• În cadrul tipului se specifică un set de
valori pe care le poate lua obiectul
(semnal, variabilă …) şi de asemenea
există şi un set de operatori (+, AND etc)
asociaţi tipului respectiv.
 Basic types
• BIT
• BOOLEAN
• BIT_VECTOR
• INTEGER
• REAL
• Std_logic
 BIT
• Tipurile bit şi bit-vector contin bit 0 si 1

• signal ina : bit;

variable inb : bit := ‘0’;
ina <= inb and inc;
ind <= ‘1’ after 10 ns;
 Boolean

• Tipul boolean are două valori true şi false

• signal test1 : Boolean;

variable test2 : Boolean := FALSE;
 integer
• Tipul integer (întreg) cuprinde domeniul
numerelor întregi incluzând domeniul
• (-2147483647 to 2147483647 )
signal int1 : integer;
variable int2 : integer := 124;
 Integer subtypes: natural
• natural values : 0 to integer’high
 Integer subtypes: positive
• positive values : 1 to integer’high
 character
• Tipul character (caracter) include toate
caracterele din setul de caractere ISO*
(International Organization of
Standardization) exprimate pe 8 biţi,
primele 128 fiind caractere ASCII
 real
• -1.0e38 to 10e38
• signal realno : real;
variable realno : real := 123.456;
 time
• -2147483647 and 2147483647 fs
• ps = 1000 fs;
ns = 1000 ps;
us = 1000 ns;
ms = 1000 us;
min = 60 sec;
hr = 60 min;

• delay : time := 10 ns;

wait for 20 us;
y <= x after 10 ms;
z <= y after delay;
 Std_logic type definition
‘U’: uninitialized; this signal hasn’t been set yet
‘X’: unknown; impossible to determine this value/result
‘0’: logic 0
‘1’: logic 1
‘Z’: High Impedance
‘W’: Weak signal, can’t tell if it should be 0 or 1
‘L’: Weak signal that should probably go to 0
‘H’: Weak signal that should probably go to 1
‘-’: Don’t care
Operatori
• Folosind operatorul concatenare & (concatenation
operator) se pot alătura elementele unei matrici în
ordinea în care sunt scrise, de la stânga la dreapta,
• de exemplu prin concatenarea ‘0’ & ’1’ & ‘1Z’ se obţine
“011Z”.
• Cel mai important tip de matrice des întâlnit în
programele VHDL este cel aparţinând standardului logic
definit de utilizator IEEE 1164 (std_logic_vector),
definiţia acestui standard este:
• type STD_LOGIC_VECTOR is array (<natural range>) of STD_LOGIC
 Concatenation
• A <= ‘1111’;
B <= ‘000’;
out1 <= A & B & ‘1’; -- out1 = ‘11110001’;
• A is a bit_vector equal to "10010101":
A sll 2 is "01010100" (shift left logical, filled with '0')
A srl 3 is "00010010" (shift right logical, filled with '0')
A sla 3 is "10101111" (shift left arithmetic, filled with
right bit)
A sra 2 is "11100101" (shift right arithmetic, filled with
left bit)
A rol 3 is "10101100" (rotate left)
A ror 5 is "10101100" (rotate right)
 Instructiuni concurente
architecture behavioural of test is
signal int1, int2 : bit;
begin
int1 <= in1 and in2;
int2 <= in3 or in4;
out1 <= int1 xor int2;
end architecture behavioural;
when
select
 Instructiuni secventiale
process (sensitivity_list) is
... declaration part
begin
... statement part
end process;
process (clk, rst) is
begin
... process statements
end process;

process (a) is
signal na : bit;
begin
na <= not a;
end process;
 If-then-else

• if (condition) then
... statements
end if;

• if ( a = b ) then
out1 <= ‘1’;
end if;
 If-then-else
• if (condition) then
... statements
else
... statements
end if;

• if ( a = b ) then
out1 <= ‘1’;
else
out1 <= ‘0’;
end if;
 If-then-else
if (condition1) then
... statements
elsif (condition2)
... statements
... more elsif conditions & statements
else
... statements
end if;
 If-then-else
if (a > 10) then
out1 <= ‘1’;
elsif (a > 5) then
out1 <= ‘0’;
else
out1 <= ‘1’;
end if;
 Case
case testvariable is
when 1 => out1 <= ‘1’;
when 2 => out2 <= ‘1’;
when 3 => out3 <= ‘1’;
end case;

case test is
when 0 to 4 => out1 <= ‘1’;

case test is
when 0 => out1 <= ‘1’;
when others => out1 <= ‘0’;
end case;
 For
for loopvar in start to finish loop
... loop statements
end loop;

for loopvar in start downto finish loop

... loop statements
end loop;
 For
signal a : std_logic_vector(7 downto 0);

for i in 0 to 7 loop
a(i) <= ‘1’;
end loop;
 While and loop
• for i in 0 to 7 loop
if ( i = 4 ) then
exit;
endif;
endloop;

• for i in 0 to 7 loop
if ( i = 4 ) then
next;
endif;
endloop;
• WHILE (day = weekday) LOOP
day := get_next_day(day);
END LOOP;
 Functions
function name (input declarations) return
output_type is
... variable declarations
begin
... function body
end
 Functions
function mult (a,b : integer) return integer is
begin
return a * b;
end;

x <= mult(a, b);

 Procedures
procedure identifier [input/output port
declarations] is
[variable declarations]
begin
procedure statements
end identifier
 Procedures

procedure full_adder (a,b : in bit; sum, carry : out bit) is

begin
sum := a xor b;
carry := a and b;
end;
 Packages
package name is
...package header contents
end package;
package body name is
... package body contents
end package body;
and10 = and(a,b,c,d,e,f,g,h,i,j)

function and10 (a,b,c,d,e,f,g,h,i,j : bit) return bit is

begin
return a and b and c and d and e and f and g and h and i and j;
end;

package new_functions is
function and10 (a,b,c,d,e,f,g,h,i,j : bit) return bit;
end;
package body new_functions is
function and10 (a,b,c,d,e,f,g,h,i,j : bit) return bit is
begin
return a and b and c and d and e and f and g and h and i and j;
end;
end;
 Components
component and4
port ( a, b, c, d : in bit; q : out bit );
end component;

d1 : and4 port map ( a, b, c, d, q );

d1: and4 port map ( a => b, b => c, c => a, d => d, q => q);
 LIBRARY
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
 Curs 6

Boolean algebra
Rules of Boolean algebra
Single-Variable Theorems
 Rules of Boolean algebra
Double-Variable Theorems
• Quine–McCluskey
• Karnaugh
 Logic gates – gates.vhd
library IEEE;
use IEEE.std_logic_1164.all;
entity gates2 is
port(
a : in STD_LOGIC;
b : in STD_LOGIC;
and_gate : out STD_LOGIC;
nand_gate : out STD_LOGIC;
nor_gate : out STD_LOGIC;
or_gate : out STD_LOGIC;
xnor_gate : out STD_LOGIC;
xor_gate : out STD_LOGIC
);
end gates2;

architecture gates2 of gates2 is

begin
---- Component instantiations ----
and_gate <= b and a;
nand_gate <= not(b and a);
or_gate <= b or a;
nor_gate <= not(b or a);
xor_gate <= b xor a;
xnor_gate <= not(b xor a);
end gates2;
 gates_top.vhd
library IEEE;
use IEEE.std_logic_1164.all;
library EXAMPLE2;
entity gates2_top is
port(
sw : in STD_LOGIC_VECTOR(1 downto 0);
ld : out STD_LOGIC_VECTOR(5 downto 0)
);
end gates2_top;
architecture gates2_top of gates2_top is
component gates2
port (
a : in std_logic;
and_gate : out std_logic;
b : in std_logic;
nand_gate : out std_logic;
nor_gate : out std_logic;
or_gate : out std_logic;
xnor_gate : out std_logic;
xor_gate : out std_logic
);
end component;
begin
U1 : gates2
port map(
a => sw(1),
b => sw(0),
and_gate => ld(5),
nand_gate => ld(4),
nor_gate => ld(3),
or_gate => ld(2),
xnor_gate => ld(1),
xor_gate => ld(0)
);
end gates2_top;
 Car alarm

S = (M D' V) + (M D V') + (M D V)
S = (M AND (NOT D) AND V) OR (M AND D AND (NOT V)) OR (M AND D
AND V)
majority
majority
 majority.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity majority4 is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : in STD_LOGIC;
d : in STD_LOGIC;
f : out STD_LOGIC);
end majority4;

architecture Behavioral of majority4 is

begin
f <= ((b and c and d) or (a and c and d) or (a and b and d)
or (a and b and c));

end Behavioral;
 majority_top.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity majority4_top is
Port ( sw : in STD_LOGIC_VECTOR (3 downto 0);
led : out STD_LOGIC_VECTOR (0 downto 0));
end majority4_top;

architecture Behavioral of majority4_top is

component majority4 is
port(
a : in STD_LOGIC;
b : in STD_LOGIC;
c : in STD_LOGIC;
d : in STD_LOGIC;
f : out STD_LOGIC);
end component;
begin
c1 : majority4
port map(
a => sw(3),
b => sw(2),
c => sw(1),
d => sw(0),
f => led(0)
);

end Behavioral;
 Curs 7
Circuite logice combinationale (1)
Comparatoare
Multiplexoare si demultiplexoare
Comparator pe 2 biti
 Comp2bit.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity comp2bit is
Port ( a : in STD_LOGIC_VECTOR (1 downto 0);
b : in STD_LOGIC_VECTOR (1 downto 0);
a_eq_b : out STD_LOGIC;
a_gt_b : out STD_LOGIC;
a_lt_b : out STD_LOGIC);
end comp2bit;

architecture Behavioral of comp2bit is

begin
a_eq_b <= (not b(1) and not b(0) and not a(1) and not a(0)) or (not b(1) and b(0) and not a(1) and
a(0)) or (b(1) and not b(0) and a(1) and not a(0)) or (b(1) and b(0) and a(1) and a(0));
a_gt_b <= (not b(1) and a(1)) or (not b(1) and not b(0) and a(0)) or (not b(0) and a(1) and a(0));
a_lt_b <= (b(1) and not a(1)) or (b(1) and b(0) and not a(0)) or (b(0) and not a(1) and not a(0));

end Behavioral;
 comp2bit_top.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity comp2bit_top is
Port ( sw : in STD_LOGIC_VECTOR (3 downto 0);
led : out STD_LOGIC_VECTOR (2 downto 0)
);
end comp2bit_top;

architecture Behavioral of comp2bit_top is

component comp2bit is
Port(
a : in STD_LOGIC_VECTOR (1 downto 0);
b : in STD_LOGIC_VECTOR (1 downto 0);
a_eq_b : out STD_LOGIC;
a_gt_b : out STD_LOGIC;
a_lt_b : out STD_LOGIC
);
end component;
begin
c1 : comp2bit
port map(
a => sw(3 downto 2),
b => sw(1 downto 0),
a_eq_b => led(1),
a_gt_b => led(0),
a_lt_b => led(2)
);

end Behavioral;
multiplexer
 Mux_v1.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mux21a is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
s : in STD_LOGIC;
y : out STD_LOGIC
);
end mux21a;

architecture Behavioral of mux21a is

Begin
y <= (not s and a) or (s and b);
end Behavioral;
 Mux_v2.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mux21b is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
s : in STD_LOGIC;
y : out STD_LOGIC
);
end mux21b;

architecture Behavioral of mux21b is

begin
p1: process (a, b, s)
begin
if s = '0' then
y <= a;
else
y <= b;
end if;
end process;

end Behavioral;
 Mux_v3.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mux21c is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
s : in STD_LOGIC;
y : out STD_LOGIC);
end mux21c;

architecture Behavioral of mux21c is

begin
y <= a when s = '0' else b;

end Behavioral;
 Mux_top.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mux21_top is
Port ( sw : in STD_LOGIC_VECTOR (1 downto 0);
btn : in STD_LOGIC_VECTOR (0 downto 0);
led : out STD_LOGIC_VECTOR (0 downto 0)
);
end mux21_top;

architecture Behavioral of mux21_top is

component mux21a is
port(
a : in STD_LOGIC;
b : in STD_LOGIC;
s : in STD_LOGIC;
y : out STD_LOGIC
);
end component;

begin
a1 : mux21a
port map(
a => sw(0),
b => sw(1),
s => btn(0),
y => led(0)
);

end Behavioral;
Mux 4 to 1
 Mux4to1_v1.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mux41b is
Port ( c : in STD_LOGIC_VECTOR (3 downto 0);
s : in STD_LOGIC_VECTOR (1 downto 0);
z : out STD_LOGIC);
end mux41b;

architecture Behavioral of mux41b is

begin
z <= (not s(1) and not s(0) and c(0)) or (not s(1) and s(0) and c(1)) or (s(1) and not s(0)
and c(2)) or (s(1) and s(0) and c(3));

end Behavioral;
 Mux4to1_v2.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mux41c is
Port ( c : in STD_LOGIC_VECTOR (3 downto 0);
s : in STD_LOGIC_VECTOR (1 downto 0);
z : out STD_LOGIC_VECTOR (0 downto 0));
end mux41c;

architecture Behavioral of mux41c is

begin
p1: process(c, s)
begin
case s is
when "00" => z(0) <= c(0);
when "01" => z(0) <= c(1);
when "10" => z(0) <= c(2);
when "11" => z(0) <= c(3);
when others => z(0) <= c(0);
end case;
end process;

end Behavioral;
library IEEE;
Mux4to1_top.vhd
use IEEE.STD_LOGIC_1164.ALL;
entity mux41b_top is
Port ( sw : in STD_LOGIC_VECTOR (3 downto 0);
btn : in STD_LOGIC_VECTOR (1 downto 0);
led : out STD_LOGIC_VECTOR (0 downto 0));
end mux41b_top;

architecture Behavioral of mux41b_top is

component mux41b is
Port (c : in STD_LOGIC_VECTOR (3 downto 0);
s : in STD_LOGIC_VECTOR (1 downto 0);
z : OUT STD_LOGIC);
end component;
begin

c1 : mux41b
port map(
c(0) => sw(0),
c(1) => sw(1),
c(2) => sw(2),
c(3) => sw(3),
s(0) => btn(0),
s(1) => btn(1),
z => led(0)
);
end Behavioral;
Mux4to1_v3.vhd
 Mux_top.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL; begin
entity mux21_top is a1 : mux21a
Port ( sw : in STD_LOGIC_VECTOR (5 downto 0);
port map(
btn : in STD_LOGIC_VECTOR (2 downto 0);
led : out STD_LOGIC_VECTOR (2 downto 0)); a => sw(0),
end mux21_top; b => sw(1),
s => btn(0),
architecture Behavioral of mux21_top is y => led(0)
component mux21a is –v1 );
port(
a : in STD_LOGIC;
b : in STD_LOGIC; b1 : mux21b
s : in STD_LOGIC; port map(
y : out STD_LOGIC a => sw(2),
); b => sw(3),
end component;
s => btn(1),
component mux21b is –v2 y => led(1)
port( );
a : in STD_LOGIC;
b : in STD_LOGIC; c1 : mux21c
s : in STD_LOGIC; port map(
y : out STD_LOGIC
);
a => sw(4),
end component; b => sw(5),
s => btn(2),
component mux21c is –v3 y => led(2)
port( );
a : in STD_LOGIC;
b : in STD_LOGIC;
s : in STD_LOGIC; end Behavioral;
y : out STD_LOGIC
);
end component;
Mux quad 2 to 1
 Mux24_v1.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mux24a is
Port ( a : in STD_LOGIC_VECTOR (3 downto 0);
b : in STD_LOGIC_VECTOR (3 downto 0);
s : in STD_LOGIC;
y : out STD_LOGIC_VECTOR (3 downto 0)
);
end mux24a;

architecture Behavioral of mux24a is

signal s4: STD_LOGIC_VECTOR(3 downto 0);
begin
s4 <= s & s & s & s; -- concatenare
y <= (not s4 and a) or (s4 and b);

end Behavioral;
 Mux24_v2.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity mux24b is
Port ( a : in STD_LOGIC_VECTOR (3 downto 0);
b : in STD_LOGIC_VECTOR (3 downto 0);
s : in STD_LOGIC;
y : out STD_LOGIC_VECTOR (3 downto 0));
end mux24b;

architecture Behavioral of mux24b is

begin
p1: process (a, b, s)
begin
if s = '0' then
y <= a;
else
y <= b;
end if;
end process;

end Behavioral;
 Mux24_v3.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mux24c is
Port ( a : in STD_LOGIC_VECTOR (3 downto 0);
b : in STD_LOGIC_VECTOR (3 downto 0);
s : in STD_LOGIC;
y : out STD_LOGIC_VECTOR (3 downto 0));
end mux24c;

architecture Behavioral of mux24c is

begin
y <= a when s = '0' else b;

end Behavioral;
 Mux24_top.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mux24_top is
Port ( sw : in STD_LOGIC_VECTOR (7 downto 0);
btn : in STD_LOGIC_VECTOR (0 downto 0);
led : out STD_LOGIC_VECTOR (3 downto 0));
end mux24_top;

architecture Behavioral of mux24_top is

component mux24a is
port(
a : in STD_LOGIC_VECTOR(3 downto 0);
b : in STD_LOGIC_VECTOR(3 downto 0);
s : in STD_LOGIC;
y : out STD_LOGIC_VECTOR(3 downto 0)
);
end component;

begin
QM1: mux24a port map
(a => SW(3 downto 0), b => SW(7 downto 4), s => BTN(0), y => LED(3 downto 0));

end Behavioral;
Dmux
 Dmux.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity dmux is
Port ( a : in STD_LOGIC;
s : in STD_LOGIC_VECTOR (1 downto 0);
y : out STD_LOGIC_VECTOR (3 downto 0));
end dmux;
architecture Behavioral of dmux is
begin
y(0) <= (not s(0)) and (not s(1)) and a;
y(1) <= (not s(0)) and s(1) and a;
y(2) <= s(0) and (not s(1)) and a;
y(3) <= s(0) and s(1) and a;
end Behavioral;
 Dmux_top.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity dmux_top is
Port ( sw : in STD_LOGIC_VECTOR (0 downto 0);
btnC : in STD_LOGIC;
btnL : in STD_LOGIC;
led : out STD_LOGIC_VECTOR (3 downto 0));
end dmux_top;
architecture Behavioral of dmux_top is
component dmux is
port( a : in STD_LOGIC;
s : in STD_LOGIC_VECTOR (1 downto 0);
y : out STD_LOGIC_VECTOR (3 downto 0));
end component;
begin
a1 : dmux
port map( a => sw(0),
s(0) => btnL,
s(1) => btnC,
y(0) => led(0),
y(1) => led(1),
y(2) => led(2),
y(3) => led(3));
end Behavioral;
 Curs 8
Circuite logice combinationale (2)

Codoare si decodoare
 Encoder

y1 = w3 + w2
y0 = w3 + w1
Priority Encoders
Priority Encoders
 Enc.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity enc4to2 is
Port ( x : in STD_LOGIC_VECTOR (3 downto 0);
y : out STD_LOGIC_VECTOR (1 downto 0);
v: out STD_LOGIC
);
end enc4to2;

architecture Behavioral of enc4to2 is

begin
process(x)
begin
y(1) <= x(3) or x(2);
y(0) <= x(3) or (not x(2) and x(1));
v <= x(3) or x(2) or x(1) or x(0);

end process;

end Behavioral;
 Enc_top.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity enc4to2_top is
Port ( sw : in STD_LOGIC_VECTOR (3 downto 0);
led : out STD_LOGIC_VECTOR (1 downto 0);
dp : out STD_LOGIC
);
end enc4to2_top;

architecture Behavioral of enc4to2_top is

component enc4to2 is
Port ( x : in STD_LOGIC_VECTOR (3 downto 0);
y : out STD_LOGIC_VECTOR (1 downto 0);
v: out STD_LOGIC
);
end component;

begin
E1: enc4to2
port map(
x => sw,
y => led,
v => dp
);

end Behavioral;
Decoder 2to4
Decoder 3to8
 Dec3to8_v1.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity dec3to8 is
Port ( a : in STD_LOGIC_VECTOR (2 downto 0);
y : out STD_LOGIC_VECTOR (7 downto 0));
end dec3to8;

architecture Behavioral of dec3to8 is

begin
y(0) <= not a(2) and not a(1) and not a(0);
y(1) <= not a(2) and not a(1) and a(0);
y(2) <= not a(2) and a(1) and not a(0);
y(3) <= not a(2) and a(1) and a(0);
y(4) <= a(2) and not a(1) and not a(0);
y(5) <= a(2) and not a(1) and a(0);
y(6) <= a(2) and a(1) and not a(0);
y(7) <= a(2) and a(1) and a(0);

end Behavioral;
 Dec3to8_v2.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
entity dec3to8 is
Port ( a : in STD_LOGIC_VECTOR (2 downto 0);
y : out STD_LOGIC_VECTOR (7 downto 0));
end dec3to8;

architecture Behavioral of dec3to8 is

begin
process (a)
variable j : integer;
begin
j := conv_integer(a);
for i in 0 to 7 loop
if (i = j) then
y(i) <= ‘1’;
else
y(i) <= ‘0’;
end if;
end loop;
end process;
end Behavioral;
 Dec3to8_top.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity dec3to8_top is
Port ( sw : in STD_LOGIC_VECTOR (2 downto 0);
led : out STD_LOGIC_VECTOR (7 downto 0));
end dec3to8_top;

architecture Behavioral of dec3to8_top is

component dec3to8 is
port( a : in STD_LOGIC_VECTOR (2 downto 0);
y : out STD_LOGIC_VECTOR (7 downto 0)
);
end component;
begin
D1: dec3to8
port map(
a => sw,
y => led
);

end Behavioral;
7-segments display
 7seg_v1.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity hex7seg_le is
Port ( x : in STD_LOGIC_VECTOR (3 downto 0);
a_to_g : out STD_LOGIC_VECTOR (6 downto 0));
end hex7seg_le;

architecture Behavioral of hex7seg_le is

begin
a_to_g(6) <= (not x(3) and not x(2) and not x(1) and x(0)) or (not x(3) and x(2) and not x(1) and not x(0)) or (x(3)
and x(2) and not x(1) and x(0)) or (x(3) and not x(2) and x(1) and x(0));
a_to_g(5) <= (x(2) and x(1) and not x(0)) or (x(3) and x(1) and x(0)) or (not x(3) and x(2) and not x(1) and x(0)) or (x(3)
and x(2) and not x(1) and not x(0));
a_to_g(4) <= (not x(3) and not x(2) and x(1) and not x(0)) or (x(3) and x(2) and x(1)) or (x(3) and x(2) and not x(0));
a_to_g(3) <= (not x(3) and not x(2) and not x(1) and x(0)) or (not x(3) and x(2) and not x(1) and not x(0)) or (x(3) and
not x(2) and x(1) and not x(0)) or (x(2) and x(1) and x(0));
a_to_g(2) <= (not x(3) and x(0)) or (not x(3) and x(2) and not x(1)) or (not x(2) and not x(1) and x(0));
a_to_g(1) <= (not x(3) and not x(2) and x(0)) or (not x(3) and not x(2) and x(1)) or (not x(3) and x(1) and x(0)) or (x(3)
and x(2) and not x(1) and x(0));
a_to_g(0) <= (not x(3) and not x(2) and not x(1)) or (x(3) and x(2) and not x(1) and not x(0)) or (not x(3) and x(2) and
x(1) and x(0));

end Behavioral;
 7seg_v2.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity hex7segb is
Port ( x : in STD_LOGIC_VECTOR (3 downto 0);
a_to_g : out STD_LOGIC_VECTOR (6 downto 0));
end hex7segb;
architecture Behavioral of hex7segb is

begin
process(x)
begin
case x is
when "0000" => a_to_g <= "0000001";
when "0001" => a_to_g <= "1001111";
when "0010" => a_to_g <= "0010010";
when "0011" => a_to_g <= "0000110";
when "0100" => a_to_g <= "1001100";
when "0101" => a_to_g <= "0100100";
when "0110" => a_to_g <= "0100000";
when "0111" => a_to_g <= "0001101";
when "1000" => a_to_g <= "0000000";
when "1001" => a_to_g <= "0000100";
when "1010" => a_to_g <= "0001000";
when "1011" => a_to_g <= "1100000";
when "1100" => a_to_g <= "0110001";
when "1101" => a_to_g <= "1000010";
when "1110" => a_to_g <= "0110000";
when others => a_to_g <= "0111000";
end case;
end process;
end Behavioral;
 7seg_top.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity hex7seg_top is
Port ( sw : in STD_LOGIC_VECTOR (3 downto 0);
a_to_g : out STD_LOGIC_VECTOR (6 downto 0);
an : out STD_LOGIC_VECTOR (3 downto 0);
dp : out STD_LOGIC);
end hex7seg_top;

architecture Behavioral of hex7seg_top is

component hex7seg_le is
port(
x: in STD_LOGIC_VECTOR(3 downto 0);
a_to_g: out STD_LOGIC_VECTOR(6 downto 0)
);
end component;
begin
an <= "0000";
dp <= '1';

D4: hex7seg_le port map(

x => sw,
a_to_g => a_to_g
);

end Behavioral;
Mux7seg
 Mux7seg.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL; --7 seg decoder
entity mux7seg is process(digit)
Port ( btn : in STD_LOGIC_VECTOR (3 downto 0); begin
a_to_g : out STD_LOGIC_VECTOR (6 downto 0); case digit is
an : out STD_LOGIC_VECTOR (3 downto 0); when X"0" => a_to_g <= "0000001";
dp : out STD_LOGIC); when X"1" => a_to_g <= "1001111";
end mux7seg; when X"2" => a_to_g <= "0010010";
architecture Behavioral of mux7seg is when X"3" => a_to_g <= "0000110";
signal x: STD_LOGIC_VECTOR(15 downto 0); when X"4" => a_to_g <= "1001100";
signal s: STD_LOGIC_VECTOR(1 downto 0);
when X"5" => a_to_g <= "0100100";
signal digit: STD_LOGIC_VECTOR(3 downto 0);
when X"6" => a_to_g <= "0100000";
Begin
when X"7" => a_to_g <= "0001101";
x <= X"1234";
when X"8" => a_to_g <= "0000000";
an <= not btn;
when X"9" => a_to_g <= "0000100";
s(1) <= btn(2) or btn(3);
s(0) <= btn(1) or btn(3);
when X"A" => a_to_g <= "0001000";
dp <= '1';
when X"B" => a_to_g <= "1100000";
--4 to 1 mux when X"C" => a_to_g <= "0110001";
process(s) when X"D" => a_to_g <= "1000010";
begin when X"E" => a_to_g <= "0110000";
case s is when others => a_to_g <= "0111000";
when "00" => digit <= x(3 downto 0); end case;
when "01" => digit <= x(7 downto 4); end process;
when "10" => digit <= x(11 downto 8); end Behavioral;
when others => digit <= x(15 downto 12);
end case;
end process;
clock
top
BCD – logic gates
BCD - algoritmic
Binary to bcd converter – binbcd8.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
entity binbcd8 is
Port ( b : in STD_LOGIC_VECTOR (7 downto 0);
p : out STD_LOGIC_VECTOR (9 downto 0));
end binbcd8;

architecture Behavioral of binbcd8 is

begin
bcd1:process(b)
variable z: STD_LOGIC_VECTOR(17 downto 0);

begin
for i in 0 to 17 loop
z(i) := '0';
end loop;
z(10 downto 3) := b;
for i in 0 to 4 loop
if z(11 downto 8) > 4 then
z(11 downto 8) := z(11 downto 8) + 3;
end if;
if z(15 downto 12) > 4 then
z(15 downto 12) := z(15 downto 12) + 3;
end if;
z(17 downto 1) := z(16 downto 0);
end loop;
p <= z(17 downto 8);
end process bcd1;
end Behavioral;
 mux7segb.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.all;
entity mux7segb is
Port ( x : in STD_LOGIC_VECTOR (15 downto
0);
clk : in STD_LOGIC;
clr : in STD_LOGIC;
a_to_g : out STD_LOGIC_VECTOR (6
downto 0);
an : out STD_LOGIC_VECTOR (3 downto
0);
dp : out STD_LOGIC);
end mux7segb;
architecture Behavioral of mux7segb is
signal s: STD_LOGIC_VECTOR(1 downto 0);
signal digit: STD_LOGIC_VECTOR(3 downto 0);
end case;
signal aen: STD_LOGIC_VECTOR(3 downto 0);
end process;
signal clkdiv: STD_LOGIC_VECTOR(20 downto 0);
begin
s <= clkdiv(20 downto 19);
dp <= '1';
-- set aen(3 downt 0) for blanks
aen(3) <= x(15) or x(14) or x(13) or x(12);
aen(2) <= x(15) or x(14) or x(13) or x(12) or x(11) or
x(10) or x(9) or x(8);
aen(1) <= x(15) or x(14) or x(13) or x(12) or x(11) or
x(10) or x(9) or x(8) or x(7) or x(6) or x(5) or x(4);
aen(0) <= '1';
--Quad 4 to 1 mux
process(s, x)
begin
case s is
when "00" => digit <= x(3 downto 0);
when "01" => digit <= x(7 downto 4);
when "10" => digit <= x(11 downto 8);
when others => digit <= x(15 downto 12);
 mux7segb.vhd (cont.)
-- 7 seg decoder --digit select
process(digit)
begin
process(s, aen)
case digit is
when X"0" => a_to_g <= "0000001“;
begin
when X"1" => a_to_g <= "1001111“; an <= "1111";
when X"2" => a_to_g <= "0010010“; if aen(conv_integer(s)) = '1' then
when X"3" => a_to_g <= "0000110“; an(conv_integer(s)) <= '0';
when X"4" => a_to_g <= "1001100“;
end if;
when X"5" => a_to_g <= "0100100“;
when X"6" => a_to_g <= "0100000“;
end process;
when X"7" => a_to_g <= "0001101“; --clk div
when X"8" => a_to_g <= "0000000“; process(clk, clr)
when X"9" => a_to_g <= "0000100“; begin
when X"A" => a_to_g <= "0001000“;
if clr = '1‘ then
when X"B" => a_to_g <= "1100000“;
when X"C" => a_to_g <= "0110001“;
clkdiv <= (others => '0');
when X"D" => a_to_g <= "1000010“; elsif clk'event and clk = '1' then
when X"E" => a_to_g <= "0110000“; clkdiv <= clkdiv + 2;
when others =>a_to_g <= "0111000"; end if;
end case; end process;
end process;
end Behavioral;
 Binbcd8_top.vhd
library IEEE; signal x: STD_LOGIC_VECTOR(15 downto 0);
use IEEE.STD_LOGIC_1164.ALL;
signal p: STD_LOGIC_VECTOR(9 downto 0);
entity binbcd8_top is
Port ( mclk : in STD_LOGIC; begin
btn : in STD_LOGIC_VECTOR (3 downto 3); x <= "000000" & p;
sw : in STD_LOGIC_VECTOR (7 downto 0);
led <= sw;
led : out STD_LOGIC_VECTOR (7 downto 0);
a_to_g : out STD_LOGIC_VECTOR (6 downto 0);
an : out STD_LOGIC_VECTOR (3 downto 0); B1: binbcd8
dp : out STD_LOGIC); port map (
end binbcd8_top;
b => sw,
architecture Behavioral of binbcd8_top is
p => p
component binbcd8 is );
port(
b : in STD_LOGIC_VECTOR(7 downto 0);
X2: mux7segb
p : out STD_LOGIC_VECTOR(9 downto 0)
);
port map (
end component; x => x,
clk => mclk,
component mux7segb is
clr => btn(3),
port(
x : in STD_LOGIC_VECTOR(15 downto 0);
a_to_g => a_to_g,
clk : in STD_LOGIC; an => an,
clr : in STD_LOGIC; dp => dp
a_to_g : out STD_LOGIC_VECTOR(6 downto 0);
);
an : out STD_LOGIC_VECTOR(3 downto 0);
dp : out STD_LOGIC
); end Behavioral;
end component;
 Curs 9

Arithmetic Circuits
Half-Adder
Full-Adder
4-bit adder
 Adder4bit.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity adder4bit is
Port ( a : in STD_LOGIC_VECTOR (3 downto 0);
b : in STD_LOGIC_VECTOR (3 downto 0);
cf : out STD_LOGIC;
ovf : out STD_LOGIC;
s : out STD_LOGIC_VECTOR (3 downto 0));
end adder4bit;

architecture Behavioral of adder4bit is

signal c: STD_LOGIC_VECTOR(4 DOWNTO 0); --carries inter

begin
c(0) <= '0';
s <= a xor b xor c(3 downto 0);
c(4 downto 1) <= (a and b) or (c(3 downto 0) and (a xor b));
cf <= c(4);
ovf <= c(3) xor c(4);

end Behavioral;
 Mux7sega.vhd
library IEEE;
architecture Behavioral of mux7sega is
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.all; signal s: STD_LOGIC_VECTOR(1 downto 0);
signal digit: STD_LOGIC_VECTOR(3 downto 0);
signal aen: STD_LOGIC_VECTOR(3 downto 0);
signal clkdiv: STD_LOGIC_VECTOR(19 downto 0);
entity mux7sega is
Port ( x : in STD_LOGIC_VECTOR (15 downto 0); begin
clk : in STD_LOGIC;
s <= clkdiv(19 downto 18);
clr : in STD_LOGIC;
aen <= "1111";
a_to_g : out STD_LOGIC_VECTOR (6 downto 0); dp <= '1';
an : out STD_LOGIC_VECTOR (3 downto 0);
dp : out STD_LOGIC); --Quad 4 to 1 mux
process(s, x)
end mux7sega; begin
case s is
when "00" => digit <= x(3 downto 0);
when "01" => digit <= x(7 downto 4);
when "10" => digit <= x(11 downto 8);
when others => digit <= x(15 downto 12);
end case;
end process;
-- 7 seg decoder
process(digit) --digit select
Begin process(s, aen)
begin
case digit is
an <= "1111";
when X"0" => a_to_g <= "0000001“;
if aen(conv_integer(s)) = '1' then
when X"1" => a_to_g <= "1001111“; an(conv_integer(s)) <= '0';
when X"2" => a_to_g <= "0010010“; end if;
when X"3" => a_to_g <= "0000110“; end process;
when X"4" => a_to_g <= "1001100“;
when X"5" => a_to_g <= "0100100“; --clk div
when X"6" => a_to_g <= "0100000“; process(clk, clr)
begin
when X"7" => a_to_g <= "0001101“;
if clr = '1' then
when X"8" => a_to_g <= "0000000“;
clkdiv <= (others => '0');
when X"9" => a_to_g <= "0000100“; elsif clk'event and clk = '1' then
when X"A" => a_to_g <= "0001000"; clkdiv <= clkdiv + 1;
when X"B" => a_to_g <= "1100000"; end if;
when X"C" => a_to_g <= "0110001"; end process;
when X"D" => a_to_g <= "1000010";
when X"E" => a_to_g <= "0110000“; end Behavioral;
when others => a_to_g <= "0111000";
end case;
end process;
 Adder4bit_top.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity adder4bit_top is
Port ( mclk : in STD_LOGIC;
btn : in STD_LOGIC_VECTOR (3 downto 3);
sw : in STD_LOGIC_VECTOR (7 downto 0);
led : out STD_LOGIC_VECTOR (0 downto 0);
a_to_g : out STD_LOGIC_VECTOR (6 downto 0);
an : out STD_LOGIC_VECTOR (3 downto 0);
dp : out STD_LOGIC
);
end adder4bit_top;
architecture Behavioral of adder4bit_top is

component adder4bit is
Port ( a : in STD_LOGIC_VECTOR (3 downto 0);
b : in STD_LOGIC_VECTOR (3 downto 0);
cf : out STD_LOGIC;
ovf : out STD_LOGIC;
s : out STD_LOGIC_VECTOR (3 downto 0));
end component;

component mux7sega is
Port ( x : in STD_LOGIC_VECTOR (15 downto 0);
clk : in STD_LOGIC;
clr : in STD_LOGIC;
a_to_g : out STD_LOGIC_VECTOR (6 downto 0);
an : out STD_LOGIC_VECTOR (3 downto 0);
dp : out STD_LOGIC);
end component;

signal x: STD_LOGIC_VECTOR(15 downto 0);

signal cf: STD_LOGIC;
signal s: STD_LOGIC_VECTOR(3 downto 0);
begin
x(15 downto 12) <= sw(7 downto 4);
x(11 downto 8) <= sw(3 downto 0);
x(7 downto 4) <= "000" & cf;
x(3 downto 0) <= s;

A1: adder4bit
port map(
a => sw(7 downto 4),
b => sw(3 downto 0),
s => s,
cf => cf,
ovf => led(0)
);

X2: mux7sega
port map(
x => x,
clk => mclk,
clr => btn(3),
a_to_g => a_to_g,
an => an,
dp => dp
);

end Behavioral;
Half subtractor
full subtractor
• E = 0 – adder
• E = 1 - subtractor
multiplicator
Mult.vhd
Mult_top.vhd
Mult_top.vhd
(cont.)
 divider
• 87 / D
div.vhd
 Curs 10

Circuite logice secventiale

SR latch
 SR latch
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity SRlatch is
Port ( S : in STD_LOGIC;
R : in STD_LOGIC;
clk : in STD_LOGIC;
q : out STD_LOGIC;
notq : out STD_LOGIC);
end SRlatch;

architecture Behavioral of SRlatch is

signal f1, f2, f3, f4: STD_LOGIC;begin
f1 <= not(S and clk);
f2 <= not(R and clk);
f3 <= not(f1 and f4);
f4 <= not (f2 and f3);
q <= f3;
notq <= f4;

end Behavioral;
D flip-flop
Edge-triggered D flip-flop
Edge-triggered D flip-flop
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Dflipflop is
Port ( clk : in STD_LOGIC;
D : in STD_LOGIC;
q : out STD_LOGIC;
notq : out STD_LOGIC);
end Dflipflop;

architecture Behavioral of Dflipflop is

signal f1, f2, f3, f4, f5, f6: STD_LOGIC;
begin
f1 <= not(f4 and f2);
f2 <= not(f1 and f5);
f3 <= not(f6 and f4);
f4 <= not(f3 and clk);
f5 <= not(f4 and clk and f6);
f6 <= not(f5 and D);
q <= f1;
notq <= f2;

end Behavioral;
D flip-flop with set and clear
D flip-flop with set and clear
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity csDflipflop is
Port ( clk : in STD_LOGIC;
set : in STD_LOGIC;
clr : in STD_LOGIC;
D : in STD_LOGIC;
q : out STD_LOGIC;
notq : out STD_LOGIC);
end csDflipflop;

architecture Behavioral of csDflipflop is

signal f1, f2, f3, f4, f5, f6: STD_LOGIC;
begin
f1 <= not(f4 and f2 and not set);
f2 <= not(f1 and f5 and not clr);
f3 <= not(f6 and f4 and not set);
f4 <= not(f3 and clk and not clr);
f5 <= not(f4 and clk and f6 and not set);
f6 <= not(f5 and D and not clr);
q <= f1;
notq <= f2;

end Behavioral;
D flip-flop with clear
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity dff is
Port ( clk : in STD_LOGIC;
clr : in STD_LOGIC;
D : in STD_LOGIC;
q : out STD_LOGIC);
end dff;

architecture Behavioral of dff is

begin
process(clk, clr)
begin
if(clr = '1') then
q <= '0';
elsif(rising_edge(clk)) then
q <= D;
end if;
end process;

end Behavioral;
D flip-flop with asynchronous set and clear
Divizor cu 2
 1 bit Register

• load = 0, q store
• load = 1, q = inp0
Reg1bita.vhd
Reg1bitb.vhd
4 bit reg
Reg4bit.vhd
N bit reg
Reg.vhd
Shift reg
Shiftreg.vhd
Ring counter
Ringcount.vhd
Curs 12

FSM
Mealy
process(port_intrare, stare_prezenta)
Begin
case stare_prezenta is
when stare0 =>
if (intrare = … ) then
port_iesire <= <valoare>;
else …
end if;
when stare1 =>
if (intrare = … ) then
port_iesire <= <valoare>;
else …
end if;
when stare2 =>
if (intrare = … ) then
port_iesire <= <valoare>;
else …
end if;
…
when others null;
end case;
end process;
Moore
process(stare_prezenta)
Begin
case stare_prezenta is
when stare0 => port_iesire <= <valoare>;
when stare1 => port_iesire <= <valoare>;
when stare2 =: port_iesire <= <valoare>;
…
when others null;
end case;
end process;
Door lock code
Doorlock_top.vhd
Doorlock_top.vhd (cont.)
Doorlock_top.vhd (cont.)
Doorlock.vhd
Doorlock.vhd (cont.)
Doorlock.vhd (cont.)
Doorlock.vhd (cont.)
semafor
Semafor_top.vhd
Semafor.vhd
Semafor.vhd
(cont.)
Semafor.vhd (cont.)
Clkdiv.vhd