Electronic design automation (EDA or ECAD) - unelte

software pentru proiectarea sistemelor electronice cum ar fi

cablajele imprimate si circuite integrate. Uneltele se folosesc
intr-un flux de proiectare cu ajutorul caruia designer-ul poate
proiecta si analiza intregul circuit.
Exemplu : KiCad software de tip
open source permite desenarea
de scheme si proiectarea
cablajului imprimat (printed
circuit boards (PCB)). Cu acest
program se poate obtine si lista de
materiale si layout-ul PCB.
Exemplu: KICAD PCB pentru o placa care are un circuit de tip FPGA.
http://en.wikipedia.org/wiki/File:Kicad_Pcbnew_screenshot.jpg
3D View http://en.wikipedia.org/wiki/File:Kicad_Pcbnew3D_screenshot.jpg
Scurt istoric:
1981 EDA incepe sa devina o industrie. Pana atunci cele mai mari
companii cum ar fi Hewlett Packard, Tektronix, si Intel, au folosit EDA
intern.
Se fondeaza companiile Daisy Systems, Mentor Graphics, si Valid
Logic Systems, referite colectiv DMV.
In urmatorii ani se specializeaza multe companii in EDA.
1984 Prima conferinta in domeniu: Design Automation Conference
1986 se introduce Verilog - high-level design language
1987 - U.S. Department of Defense creaza VHDL.
- se dezvolta simulatoarele care permit simularea directa
Uneltele EDA se folosesc de asemenea pentru proiectare folosind
circuite FPGA.
Software pentru Design
High-level synthesis(syn. behavioural synthesis, algorithmic
synthesis) pentru circuite digitale
Logic synthesis translation de la nivelul abstract, descris in limbaj
HDL cum ar fi Verilog sau VHDL in netlist de porti logice
Schematic Capture pentru celule standard digitale, analogice, cum
ar fi Capture CIS in Orcad by CADENCE si ISIS in Proteus
Layout cum ar fi Layout in Orcad by Cadence, ARES in Proteus
Simulare
Transistor simulation simulare low-level tranzistor
Logic simulation digital-simulation la nivel RTL sau gate-netlist
digital (boolean 0/1)
Behavioral Simulation simulare de nivel inalt la nivel de
arhitectura.
Hardware emulation hardware special pentru o emulare logica
pentru un design specific. in-circuit emulation.
Technology CAD simulare si analiza pentru un proces tehnologic.
Analiza si verificare
Verificare functionala
Clock Domain Crossing Verification (CDC check): - unelte
specializate in detectarea pierderilor de date, instabilitati
Verificare model
Equivalence checking: comparatie intre descrierea la nivel RTL- si
descrierea la nivel de porti logice sintetizabile pentru a asigura o
functionare echivalenta la nivel logic.
Static timing analysis: analiza a timpilor pentru un circuit intr-o
maniera independenta de iesiri, se determina cazul cel mai
defavorabil pentru toate intrarile posibile.
Physical verification, PV: verificare daca un design este fizic
fabricabil, fara defecte si care sa aibe specificatiile originale.
Pregatirea procesului de fabricatie
Mask data preparation, MDP: - generare masti litografice specifice
fabricarii fizice a circuitelor.
Resolution enhancement techniques, RET metode pentru cresterea
calitatii a mastilor.
Optical proximity correction, OPC compensare efecte de difractie,
interferente care apar la fabricarea cipului folosind mastile
Mask generation generare imagine pentru masca pentru proiecte
care folosesc ierarhiile.
Automatic test pattern generation, ATPG pattern-uri pentru
componente repetitive..
Built-in self-test, BIST controllere de test pentru testarea automata
a logicii intr-un proiect.
AUTOMATIZARE FPGA DESIGN
MathWorks Matlab, Simulink solutii pentru FPGA design
Accelerare proiectare FPGA modelare, analiza, generare cod HDL si verificare
Folosind un model in Simulink - se poate genera cod HDL independent de device,
optimizat
Simulink este un mediu de simulare multidomeniu i de design bazat pe model
(Model-Based Design ) pentru sisteme dinamice i integrate.
ofer un mediu interactiv grafic i un set de biblioteci
permite proiectarea, simularea, punerea n aplicare, testarea pentru diferite sisteme,
inclusiv de comunica ii, control, procesare de semnal, prelucrare video, i de procesare
a imaginii.
http://www.mathworks.com/products/simulink/ - prezentare Simulink
Simulink HDL Coder - genereaza automat codul HDL pentru punerea n aplicare
rapid a algoritmilor n FPGA. Se poate verifica func ional codul HDL prin utilizarea
EDA Simulator Link pentru a conecta un stand de ncercare Simulink cu
implementarea FPGA care ruleaz ntr-un simulator de HDL.
Generare cod HDL sintetizabil
Cu Simulink HDL Coder se poate automatiza generarea unui cod VHDL
sau Verilog pornind de la modelul proiectat care va putea fi sintetizat pentru
implementarea in FPGA.
Codul Verilog sau VHDL se poate genera plecand de la un model Simulink
sau de la cod Matlab.
Codul generat se poate folosi intr-un proiect pentru circuite reconfigurabile
urmand procesele de sinteza,translatare, mapare, plasare, rutare si
configurare FPGA.
1. Se modeleaza sistemul folosind Simulink sau cod Matlab sau diagrame
de stare.
2. Se configureaza diferiti parametri pentru a selecta diferite blocuri de
implementare HDL.
3. Se optimizeaza modelul
4. Generare cod HDL folosind HDL Workflow Advisor sau
Configuration Parameters GUI
Se verifica codul generat prin folosirea formelor de unda de test
Generare HDL cod plecand de la cod Matlab se foloseste
Embedded MATLAB

in Simulink.
Simulink HDL Coder furnizeaza o biblioteca care are elemente de logica uzuale, cum
ar fi numaratoare, timere etc. care sunt scrise in cod Matlab.
Automating FPGA Design
Fluxul de proiectare FPGA design folosind Simulink HDL Coder
HDL Workflow Advisor foloseste unelte de sinteza cum ar fi Xilinx ISE si Altera
Quartus II.
Simulink HDL Coder permite integrarea rapida a modelului Simulink
in circuitele de tip FPGA de la Xilinx sau Altera.
HDL Workflow Advisor permite integrarea tuturor proceselor
specifice FPGA
Verificarea modelului Simulink pentru compatibilitatea cu
generarea codului HDL.
Generarea codului RTL, si test bench,
Sinteza si analiza timpilor pentru integrarea folosind Xilinx ISE

si Altera Quartus

II
Furnizarea unui raport pentru resurse estimate
HDL Workflow Advisor
Se poate vizualiza un raport privind timpii post-sinteza si se poate identifica pe
modelul Simulink unde se afla constrangerile de timpi si problemele de
bottlenecks .
Simulink HDL Coder 2.0
System Requirements
Product Requirements
Requires MATLAB
Requires Simulink
Requires Fixed-Point Toolbox
Requires Simulink Fixed Point
Signal Processing Toolbox recommended
Filter Design Toolbox recommended
Stateflow recommended
Signal Processing Blockset recommended
Filter Design HDL Coder recommended
EDA Simulator Link recommended
Communications Blockset recommended
Not available on Mac OS X, Intel Mac
Related Products
Simulink
Simulation and Model-Based Design
EDA Simulator Link
Electronic design automation
Cosimulate and verify VHDL and Verilog using HDL simulators
Filter Design HDL Coder
Generate HDL code for fixed-point filters
Communications Blockset
Design and simulate the physical layer of communication systems
Signal Processing Blockset
Design and simulate signal processing systems
Stateflow
Design and simulate state machines and control logic
Seminars
FPGA Design of Signal Processing and Communications Systems using
MATLAB and Simulink
Seminar Overview
Join us for this free half-day seminar to discover how you can reduce the time it
takes to design complex signal processing and communications systems on, and
streamline the process for optimizing the hardware performance of your FPGA
designs.
In this seminar, engineers from MathWorks will demonstrate the use of
MATLAB and Simulink to design and generate efficient system
implementations on FPGAs from algorithm and system modeling and HDL
code generation to design verification and hardware implementation.
Who Should Attend
This free seminar is recommended to engineers who are currently working on implementing
signal-processing and communications algorithms in FPGAs, or are considering the use of
FPGAs for an upcoming project; including:
Signal Processing Systems Engineers
Communications Systems Engineers
FPGA Design Engineers
FPGA Verification Engineers
Hardware Design Engineers
Hardware Verification Engineers
Prior knowledge of MathWorks products is not required.
Seminar Highlights
Topics to be discussed include:
Introduction to MATLAB, Simulink and Model-Based Design
Fixed-Point Considerations
Automatic HDL Code Generation using Simulink HDL Coder
Critical Path Analysis and Pipelining
Area Efficient Implementations
Continuous Verification and Optimization
HDL Co-simulation and FPGA in the Loop to Reduce Verification Time
http://www.mathworks.com/products/demos/hdlcoder/
introduction-simulink-hdl-coder/?s_v1=22960229_1-6GO64F
Reconfigurable computing arhitectura care combina flexibilitatea
oferita de software
cu performantele oferite de hardware prin folosirea unor circuite
flexibile, de viteza mare de calcul cum ar fi circuitele de tip FPGA -
field-programmable gate arrays
Sistemele de calcul reconfigurabile se impart in 2 categorii:
sisteme hibride
Sisteme integral bazate pe circuite de tip FPGA.
Sistemul hibrid combina un singur sau mai multe circuite
reconfigurabile de tip FPGA, cu un microprocesor standard. Simplificat,
sunt arhitecturi Von-Neumann cu un accelerator FPGA.
Sisteme integral bazate pe circuite de tip FPGA. nu contin CPU, sau
daca exista etse folosit numai pentru interfatare. Avantaj sistemul de
magistrale si intreaga arhitectura elimina dezavantajele sistemelor clasice
(bottlenecks pentru arhitectura von Neumann)
Programarea sistemelor de calcul reconfigurabile
Reconfigurarea FPGA se realizeaza prin folosirea limbajelor de
descriere hardware (HDL), care poate fi generat direct sau prin
folosirea uneltelor software de tip electronic design automation
("EDA")
Reconfigurable computing Exemplu de publicatie: International Journal of
Reconfigurable Computing http://www.hindawi.com/journals/ijrc/ Table of Contents
2011
* A Vector-Like Reconfigurable Floating-Point Unit for the Logarithm, Nikolaos Alachiotis
* On Self-Timed Circuits in Real-Time Systems, Markus Ferringer
* An FPGA-Based Adaptable 200 MHz Bandwidth Channel Sounder for Wireless
Communication Channel Characterisation, David L. Ndzi, Kenneth Stuart, Somboon * The
Potential for a GPU-Like Overlay Architecture for FPGAs, Jeffrey Kingyens and J. Gregory
Steffan
* An NoC Traffic Compiler for Efficient FPGA Implementation of Sparse Graph-Oriented
Workloads, Nachiket Kapre and Andr Dehon
A Streaming High-Throughput Linear Sorter System with Contention Buffering, Jorge Ortiz
and David Andrews
* Dynamic Reconfigurable Computing: The Alternative to Homogeneous Multicores under
Massive Defect Rates, Monica Magalhes Pereira and Luigi Carro
* Reconfiguration Techniques for Self-X Power and Performance Management on Xilinx
Virtex-II/Virtex-II-Pro FPGAs, Christian Schuck, Bastian Haetzer, and Jrgen Becker
* Floorplacement for Partial Reconfigurable FPGA-Based Systems, A. Montone, M. D.
Santambrogio, F. Redaelli, and D. Sciuto
Exemple de grupuri:
Department of Computer and Electrical Engineering
University of Massachusetts
Amherst, MA 01003
Desrierea grup:
The Reconfigurable Computing Group is under the direction of Professor
Russell Tessier and focuses on a variety of topics in reconfigurable
computing including CAD for FPGAs, adaptive systems on a chip, and
adaptive implementations of communication coding in reconfigurable
hardware.
http://www.ecs.umass.edu/ece/tessier/rcg/index.html
Research
Research in RCG is mainly focused on reconfigurable computing,
FPGAs, and embedded systems. Results of this work have been
published at leading conferences and journals. Some current projects
include:
FPGA-Based Network Virtualization
Monitor Network-on-Chip
VLIW Compilation (Very Long Instruction Word (VLIW)
processor)
FPGA Parallel Soft Processing
Reconfigurable Computing Applications
Engineering Research Center
Completed projects include:
Computer-Aided Design Tools for FPGAs
Logic Emulation
FPGA Fault Tolerance and Test
Reconfigurable Architectures
Embedded System Modeling
Embedded System Security
Exemplu pentru aplicatii sisteme recofigurabile realizate de grupul de
cercetare:
-folosind paralelismul si specificatiile arhitecturilor reconfigurabile, cum
ar fi circuitele de tip FPGA, s-au dezvoltat o serie de algoritmi.
-Un astfel de exemplu este dezvoltarea unui sistem dinamic
reconfigurabil, folosit in comunicatii si arii de senzori la distanta. Un
decodor adaptiv de tip Viterbi logica dezvoltata folosind Xilinx
XC4036 (Annapolis Microsystems WildOne board). Sistemul foloseste
la decodificarea unor date.
-Un decodor dinamic reconfigurabil a fost dezvoltat folosind Altera
Stratix-based NIOS Development Board. Sistemul foloseste
reconfigurarea dinamica pentru a economisi putere.
-Sistemul combina folosirea unui FPGA cu un microcontroller, interfata
retea, interfata disc, achizitie de date.
Tipuri de sisteme multi-FPGA
Sisteme specializate multi-FPGA.
Se realizeaza legeturile intre circuitele FPGA pentru a
realiza un anumit scop.
Sisteme reutilizabile multi-FPGA system.
Emulatoare, alte sisteme pentru debugging.
Interfatare pentru sisteme de calcul
sistemele multi-FPGA sunt sisteme de calcul paralel in
sensul traditional
Este importanta granularitatea si comunicarea
Posibile scenarii in sisteme
Tipuri de retele
Ad hoc potrivite pentru sisteme specializate
Crossbar conectate 100%
Specialized crossbars.
Multi-stage.
Nu se utilizeaza in mod uzual in sistemele multi-FPGA.
FPGA FPGA FPGA
FPGA FPGA FPGA
FPGA FPGA FPGA
Interconectare de tip cel mai apropiat vecin
Avantaje:
Uniformitatea: Toate
circuitelesunt la fel
Usor de realizat in PCB.
Dezavantaje:
Rutarease poateblocausor
Se poatelimitautilizarea
logicii din FPGA
intarzieri neprevazute.
Nu se pot extindeierarhic cu
usurinta
Crossbar
Conectareintegrala:
sursa/destinatiesingulara.
Multi-point.
n
2
arie.
a b c d
w
x
y
z
Field-programmable Interconnect Components = FPICs
Arie programabila de interconectare
f. buna
conectivitate
interna
Topologie Full Crossbar
CircuiteleA-D se folosesc
numai pentru rutare
Performante predictibile
Se pot pierderesursela
conexiunilecu cel mai apropiat
vecin
Hierarchical Crossbar
Conectivitatea full
apare la nivelul de top
Rutarea intre FPGA-
uri necesita
determinarea nivelului
la care sursa si
destinatia impart un
stramos.
Simplifica rutarea
Two-level Hierarchy
Semnalele inter-FPGA
traverseaza cel mult 2
circuite de tip FPICs
O aplicatie tipica a sistemelor multi-FPGA Logic
Emulation.
O abordare in verificarea functionalitatii unui nou ASIC
-Simularea foloseste un microprocesor pentru a
verifica functionalitatea unui device.
-Emularea implementarea fizica a unui design
folosind un FPGA
LUT
Alte aplicatii : algoritmi pentru bioinformatica
Reconfigurable Computing - Division of Engineering, Brown University
BioccelerationLtd. , a bioinformatics company, is the
leading provider of systems and solutions for accelerating
searches in protein and nucleic acids databases.
Sistem multi_FPGA 8 circuite FPGA
Hardware Technology and Operation
The BioXL/H firmware is programmed into XilinxTMField
Programmable Gate Arrays (FPGA's), shown in Figure 2 as
modules. The modules on a board are connected in a ring,
making the result of each cell update available for the following
processor, which needs it according to the algorithm.
Each BioXL/H board contains eight FPGA modules and
128MB of global memory.
Each of the modules is programmed to calculate four matrix
cells per clock cycle (for the Smith-Waterman algorithm).
The clock rate of the system is 25-33MHz (programmable).
http://www.biocceleration.com/BioXLH-technical.html
Each module has its own local memory used to store the search query.
The board global memory is used to store currently searched database
sequences and search results.
Databases are transferred to BioXL/H through the network interface.
Database information is stored in the global memory of processing
boards and on the internal disk. The search calculations are performed
concurrently with the database transfer into board memory and to the
internal disk (the "streaming" mode). Databases that can fit into the
combined global memory of all boards remain in the memory for
subsequent searches (the "memory" mode). Larger sequence databases,
such as GenBank, are read from the internal disk in subsequent searches
(the "disk" mode).
At its current full speed, BioXL/H-8 rate of calculation is:
(4 updates/module)x(8 modules/board)x(8 boards)x28.7MHZ = 7.34
billion MCPS
TimeLogic http://www.timelogic.com/
DeCypher FPGA Biocomputing Systems
DeCypher delivers faster results and has better density, reliability and
cost of operation than CPU-clusters for annotating novel sequences
and assemblies against rapidly expanding genomics data resources.
DeCypher may include up to
seven SeqCruncher
FPGA devices within a
single 4U server for
excellent search
performance and
tremendous computing
density and linear
performance gains. Multiple
accelerated nodes with over
50 FPGA devices can be
clustered for supercomputer-
level performance.
SeqCruncher PCIe Accelerator Card
Designed to handle the explosion of data generated by next-generation
sequencing platforms, TimeLogic's SeqCruncher accelerator is an
entirely new circuitboard design that leverages the speed of new Xilinx
FPGA chips and the PCIe data bus. The SeqCruncher delivers 3-10X
better performance compared to our previous generation FPGA
accelerator card. HMM tests completed on one SeqCruncher ran 550X
faster than HMMer software tests completed on one 2.66 Ghz Xeon CPU
core.
CodeQuest is a biocomputing workstation that processes large
genomics searches and sophisticated informatics workflows
The CodeQuest workstation combines optimized algorithms, powerful
hardware acceleration, and PipeWorks visual workflow software to
drive your genome exploration and drug discovery research. With the
new SeqCruncher accelerator, CodeQuest is 3-30X faster than the model
it replaces. CodeQuest is an effective solution for bioinformatics experts
and novices alike. You can build and process genomic analyses without
tedious scripting and achieve compute-cluster performance, all in a
desktop solution that can be shared by the entire lab.
Intel - http://embedded.communities.intel.com/
procesor Atomconfigurabil,
FPGA + Intel Atom = Configurable Processor
Cunoscut si sub denumirea de cod Stellarton,
Chipul este compus dintr-un procesor AtomE600 i un dispozitiv FPGA
Altera, fapt care ofer o libertate n plus pentru utilizatorii ce doresc s
ncorporeze sisteme I/O proprietare i permite dezvoltatorilor s
diferen ieze astfel design-ul, sistemul oferind posibilitatea de a face
modific ri rapide, n func ie de necesit i.
The Intel Atom processor E6x5C series.
Se micsoreaza lista de materiale necesare pentru un sistem (BOM bill-of-materials)
procesorul este disponibil de la 600 MHz la 1.3 GHz.
FPGA = Altera Arria II GX care se poate programa utilizand resurse standard
Quartus II
60,000 elemente logice (LE), 3.125-Gbps transivere, 312 inmultitoare
FPGA-ul este fabricat in tehnologie 40-nm, gama de temperaturi 40 C to +85 C
Primul produs care incorporeaza noul procesor este Kontron MICROSPACE* MSMST
PCIe/104* single board computer (SBC) vizeaza aplicatii medicale, comunicatii.
1.3 GHz Intel Atom processor E665CT, pana la 2 GB de RAM, 2 SATA 2 interfete
USB 2.0.
I/O pot fi expandate folosind FPGA, folosind IP cores pentru CAN-bus, serial interfaces
(SPI Master / UART), PCI-Express, IC and GPIO.
Bibliografie:
ECE 636 Reconfigurable Computing
http://en.wikipedia.org/wiki/Reconfigurable_computing_terminology
http://www.mathworks.com/products/simulink/ - prezentare Simulink
http://ic.engin.brown.edu
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