Proiect Verilog

,,Gheorghe Asachi Ias, i
Universitatea tehnica
s, i Calculatoare
Facultatea de Automatica
Specializarea Calculatoare
Proiect Sintez
a s, i optimizare logic
a
Student, i:
Glca S, tefan(1404A)
Rotari Dumitru(1404A)
Gavrilut, a Emanuel(1405B)
Proiectarea unui sistem secvent, ial

multifunct, ional
Cont, inut
1 Enunt, problem
a
2 Algoritm
3 Schem
a logic
a
4 Rezultate
5 Cod
5.1
5.2
5.3
5.4
verilog
registru.v . . . . .
slc.v . . . . . . . .
functie.v . . . . . .
microsecventiator.v
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3
3
4
5
6
1 Enunt, problem
a
Sa se proiecteze s, i s
a se implementeze n Verilog un sistem secvent, ial care are ca intrari o variabil
a
pe 8 bit, i x s, i o intrare de select, ie a operat, iei pe 2 bit, i.
Operat, iile sunt dup
a cum urmeaz
a:
C1C0 Operat, ie
00
9x-1
01
7x-1
10
3x-1
11
x2 1
2 Algoritm
Pas1: citeste X si C
Pas2 :
if C = 01 then
i7
else if i = 10 then
i3
else if i = 11 then
ix
end if
Pas3 : R 0
Pas4: U x
Pas5 : U U 1; R R + 1
Pas 6 :
if U 6= 0 then
goto Pas4
end if
Pas7: i i 1
Pas8:
if i 6= 0 then
goto Pas5
end if
Pas9:
if C = 10 then
RR1
end if
Pas10: STOP
3 Schem
a logic
a
s0
ST
s1
R 0
si plC
s2
incR AND
decU
s3
U X
s4
0
0
U=0
s5
C C 1
s5p
C=0
s6
decR
s7
0
ST
4 Rezultate
Exemplu pentru x=2 s, i operat, ia x2 :
Exemplu pentru x=2 s, i operat, ia 3x 1:
5 Cod verilog
5.1 registru.v
module registru(datain,clk,reset,pl,inc,dec,dataout,tco);
parameter SIZE;
input [SIZE-1:0] datain;
input clk;
input reset;
input pl;
input inc;
input dec;
output [SIZE-1:0] dataout;
output tco;
reg [SIZE-1:0] dataout;
reg tco;
always @(posedge clk)
begin
tco = 0;
casex(reset,pl,inc,dec)
4b1xxx:dataout=0;
4b01xx:dataout=datain;
4b0010:dataout=dataout +1;
4b0001:dataout=dataout -1;
endcase
if(dataout==8h00)
tco=1b1;
end
endmodule
module test_reg;
reg[15:0] datain;
reg clk,reset,pl,dec,inc;
wire[15:0] dataout;
wire tco;
registru #(16) reg_inst(.datain(datain),.clk(clk),.reset(reset),
.pl(pl),.inc(inc),.dec(dec),.dataout(dataout),.tco(tco));
initial
begin
#0 clk = 0;
forever #5 clk = ~clk;
end
initial
#150 $finish;
initial
begin
#0 reset=0;
#20 datain = 16h0004;pl=1; dec=1b1;inc=0;
#20 pl=1b0;
#60 inc=1;
end
endmodule
5.2 slc.v
module slc(x,c,out);
input [7:0]x;
input [1:0]c;
output [7:0]out;
reg [7:0]out;
always @(c or x)
begin
case(c)
2b00: out=8d9;
2b01: out=8d7;
2b10: out=8d3;
2b11: out=x;
endcase
end
endmodule
5.3 functie.v
module functie(clk,st,c,x,rez,ready);
input [1:0]c;
input [7:0]x;
input clk,st;
output [15:0]rez;
supply0 gnd;
output ready;
wire [7:0]slcx;
wire plx;
wire [7:0]datax;
wire [7:0]datau;
wire [7:0]datac;
wire tcox,tcoc,tcou,tcor;
wire plu,decu;
wire plc,decc;
wire resetR,incr,decr;
wire [15:0]datainr;
slc slc_inst(.x(x),.c(c),.out(slcx));
registru #(8) reg_x(.datain(x),.clk(clk),.reset(gnd),.pl(plx),.inc(gnd),.dec(gnd),.dataout(data
registru #(8) reg_u(.datain(datax),.clk(clk),.reset(gnd),.pl(plu),.inc(gnd),.dec(decu),.dataout
registru #(8) reg_c(.datain(slcx),.clk(clk),.reset(gnd),.pl(plc),.inc(gnd),.dec(decc),.dataout(
registru #(16) reg_rez(.datain(datainr),.clk(clk),.reset(resetR),.pl(gnd),.inc(incr),.dec(decr)
microsec microsec_inst(.clk(clk), .st(st),.u0(tcou),.c0(tcoc),.resetR(resetR),.plU(plu),.plX(pl
.decR(decr),.ready(ready),.plc(plc),.decc(decc));
endmodule
module test_functie;
reg clk,st;
reg [1:0]c;
reg[7:0]x;
wire [15:0]rez;
wire ready;
functie functie_instanta(.clk(clk),.st(st),.c(c),.x(x),.rez(rez),.ready(ready));
initial
begin
#0 clk = 0;
forever #5 clk = ~clk;
end
initial
#500 $finish;
initial
begin
#0 st=1b1;x=8h02;c=2b11;
#10 st=1b0;
#190 st=1;c=2b10;
end
endmodule
5.4 microsecventiator.v
module microsec(clk, st,u0,c0,resetR,plU,plX,incR,decU,decR,ready,plc,decc);
input clk,st,u0,c0;
output resetR,plU,plX,incR,decU,decR,ready,plc,decc;
reg resetR,plU,plX,incR,decU,decR,ready,plc,decc;
reg [3:0]state;
parameter zero=0, unu=1, doi=2, trei=3, patru=4, cinci=5, sase=6, sapte=7, opt=8, cinciP = 9;
initial state=zero;
always @(state)
begin
case (state)
zero:
begin resetR=0;plU=0;plX=1;incR=0;decU=0;decR=0;ready=0;plc=0;decc=0; end
unu:
doi:
begin resetR=0;plU=1;plX=0;incR=0;decU=0;decR=0;ready=0; plc=0;decc=0;end
trei:
patru:
cinci:
cinciP:
sase:
sapte:
default:
endcase
end
always @(posedge clk )
begin
case (state)
zero:
if(st)
state=unu;
else
state=zero;
unu:
state=doi;
doi:
state=trei;
trei:
state = patru;
patru:
if(u0)
state=cinciP;
else
state=trei;
cinciP:
state=cinci;
cinci:
if(c0)
state=sase;
else
state=doi;
sase:
state=sapte;
sapte:
state = zero;
default:state=zero;
endcase
end
endmodule

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,,Gheorghe Asachi Ias, i

Proiectarea unui sistem secvent, ial

Exemplu pentru x=2 s, i operat, ia 3x 1:

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