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Modul VHDL corespunde unui bloc logic (component) i este compus din:
descriptorul de entitate entity descrie interfaa modulului VHDL
descriptorul de arhitectur architecture descrie funcionalitatea modulului
Librrie +
pachet
Interfaa:
Funcionalitatea:
IEEE.numeric_bit
IEEE.numeric_std
IEEE.std_logic_1164
IEEE.std_logic_unsigned
IEEE.std_logic_signed
IEEE.std_logic_arith
IEEE.std_logic_textio
IEEE.math_real
IEEE.math_complex
A <= B or C
Exemplu:
Operatori predefinii:
Exemplul 1: Exemplul 2:
Exemplul 3:
Exemplul 4:
not b 000
a & (not b) 110000 {concatenare}
c ror 2 101001
[a & (not b)] or (c ror 2) 111001
[a & (not b)] or (c ror 2) = 111001 TRUE
Instruciunea ifelse
Instruciunea when
Instruciunea with
Instruciunea case
Instruciunea loop
Cout XY XC in YC in
Sum X Y C in
entity FullAdder is
port (X, Y, Cin: in bit; --Inputs
Cout, Sum: out bit); --Outputs
end FullAdder;
0 X X 0000 Reset
1 0 X DCBA ncarc
1 1 0 QDCBA Menine
1 1 1 QDCBA + 1 Numr
1 X X X 0000 Reset
0 0 X X DCBA ncarc
0 1 1 QDCBA + 1 Numr ascendent
0 1 1 QDCBA - 1 Numr descendent
process (clk)
begin
if clkevent and clk=1
then
Q1 <= Q3 after 5 ns;
Q2 <= Q1 after 5 ns;
Q3 <= Q2 after 5 ns;
end if;
end process;
library IEEE;
use IEEE.numeric_bit.all;
entity r7495 is
port (Mode,SER,Clk1,Clk2: in bit;
D: in unsigned(3 downto 0);
Qout: out unsigned(3 downto 0));
end r7495;
architecture b7495 of r7495 is
signal Q: unsigned(3 downto 0); -- Q is the counter register
begin
process (Clk1, Clk2)
begin
if Mode='0' and Clk1'event and Clk1 = 0' then
Qout <= Qout(2 downto 0) & SER;
elsif Mode= '1' and Clk2'event and Clk2 = 0' then
Qout <= D;
end if;
end process;
end b7495;
instantiation-name: component-
lista de mapare name port map
(mapping-list);
Cascad de 4
celule sumatoare
complete pe 1 bit
Sumtorul
complet
pe 1 bit
component FullAdder
port (X, Y, Cin: in bit; -- Inputs Cout,
Sum: out bit); -- Outputs
end component;
library IEEE;
use IEEE.numeric_bit.ALL;
entity eight_bit_counter is
port (ClrN, LdN, P, T1, Clk: in bit;
Din1, Din2: in unsigned(3 downto 0);
Count: out integer range 0 to 255;
Carry2: out bit);
end eight_bit_counter;
architecture cascaded_counter of eight_bit_counter is
component c74163
port (LdN, ClrN, P, T, Clk: in bit;
D: in unsigned(3 downto 0);
Cout: out bit;
Qout: out unsigned(3 downto 0));
end component;
signal Carry1: bit;
signal Qout1, Qout2: unsigned(3 downto 0);
begin
ct1: c74163 port map (LdN, ClrN, P, T1, Clk, Din1, Carry1,
Qout1);
ct2: c74163 port map (LdN, ClrN, P, Carry1, Clk, Din2, Carry2,
Qout2);
Count <= to_integer(Qout2 & Qout1);
end cascaded_counter;
Sisteme cu circuite integrate digitale Limbajul de descriere de circuit VHDL 33
VHDL descriere comportamental
Exemplu Bistabil D
Care este interfaa bistabilului D o intrare de tact, o intrare de date, o intrare
de reset asincron i dou ieiri
Cum funcioneaz bistabilul D la frontul de tact, nivelul logic de la intrare este
transferat spre ieire
entity Sate_Machine is
port (a, CLK: in bit
State: out integer range 0 to 3);
end State_Machine;
C. H. Roth, L.K. John, Digital System Design using VHDL, Cengage Learning, 2008.
H. Kaeslin, Digital Integrated Circuit Design From VLSI Architecture to CMOS Fabrication,
Cambridge University Press, 2008.
Rabaey J.M., Chandrakasan A., Nikolic B. Digital Integrated Circuits. A design perspective.
Prentice Hall, 2003.
Jan Van der Spiegel, VHDL Tutorial, University of Pennsylvania, 2010
Ercegovac, M., Lang T., Moreno J. Introduction to Digital Systems. John Wiley &Sons Inc,
New-York, 1999
VHDL Reference Guide, Xilinx, Inc., 1999 (available on line: http://toolbox.xilinx.com/docsan/
(select Foundation Series)
Mihaela Cirlugea. Sorin Hintea. Introducere in VHDL. Casa Cartii de Stiinta. Cluj-Napoca,
1999
http://esd.cs.ucr.edu/labs/tutorial/