SISTEME CU CIRCUITE INTEGRATE DIGITALE (EA II)

ELECTRONICA DIGITALA (CAL I)

Prof.univ.dr.ing. Oniga Ștefan

Clasificarea circuitelor numerice
 Circuitele logice programabile

Circuitele logice programabile (Programmable Logic Devices - PLD) sunt

CI care conțin un număr mare de blocuri cu un număr foarte mare de porți
logice și flip-flopuri care pot fi configurate cu ajutorul unui software pentru a
realiza o anumită funcție logică complexă.
Principalele tipuri de CLP-uri sunt:

SPLD: (Simple PLDs) CLP simple au apărut primele și au un

număr mic de porți. (PLA, PAL și GAL).
CPLD: (Complex PLDs) CLP complexe sunt practic arii de
SPLD-uri interconectate pe un singur chip.
FPLD: (Field Programmable Gate Array) sunt dispozitive
programabile complexe, mai flexibile decât circuitele CPLD, cu
un număr mult mai mare de porți logice echivalente.
Circuite logice programabile

Avantajele CLP:

▪ Complexitate redusă a circuitelor imprimate

• Consum mai mic de putere
• Spațiu ocupat mai mic
• Procedee de testare mai simple
▪ Siguranță mai mare în funcționare
▪ Flexibilitatea mai mare a proiectării
Circuitele Programmable Array Logic (PAL)

O arie tipică constă dintr-o matrice de conductoare conectate în linii și

coloane la o poartă ȘI.

A A B B
Circuitele PAL au o
arie de conexiuni
programabile OTP (one
X
time programmable), în
care unele fuzibile sunt
arse permanent,
ducând la formarea
termenilor produs în Aria AND-OR simplificată
aria ȘI.
Circuitele Programmable Array Logic (PAL)

Circuitele PAL sunt programate cu dispozitive speciale de programare

care ard fuzibilele selectate. După arderea fuzibilelor, circuitul rezultant
reprezintă expresia logică Booleană a circuitului dorit.

A A B B

Ce funcție reprezintă X

circuitul programat din

figură?

X = AB + AB
Figura reprezintă funcția XOR.
Circuitele GAL (Generic Array Logic)

Circuitul GAL (Generic Array Logic) este similar cu PAL dar poate fi
reprogramat. De aceea ele sunt utile pentru dezvoltarea produselor noi
(prototipaj).

A A B B

GAL dezvoltate de
Lattice Semiconductor.
Viteză mare, pot fi
X
interfațate atât cu
circuitele de 3,3 V cât
și cele de 5 V.
 Circuitele PAL și GAL

Circuitele PAL și GAL pot fi reprezentate simplificat.

O singură linie poate reprezenta mai multe intrări. Circuitul din figură
reprezintă poarta XOR.

Input buffer A A B B
O singură linie tăiată poate
înlocui reprezentarea a mai
multor intrări ale porții ȘI

Siguranță arsă

2 AB
X X
Siguranță intactă AB + AB

X X 2
AB
 Circuitele PAL și GAL

-Dispun de arii logice extinse și circuite de ieșire care au complexitate

variabilă. Logica de ieșire este conectată la fiecare poartă SAU și
împreună formează o așa numită macrocelulă.
- Sunt prezentate două tipuri de macrocelule PAL/GAL

Tristate control

From From
AND I/O AND I/O
array array
To AND To AND
array array
Legătură programabilă
controlează polaritatea
ieșirii (directă sau negată)
 Exemplu de circuit PAL
7
I1 Macrocell O1

Circuitul PAL16V8 este un CLP I2 7

simplu tipic. El dispune de 16 pini

Macrocell I/O1

de intrare și 8 pini de ieșire. Pinii I3

7
I/O pins ocupă atât un pin de ieșire Macrocell I/O2
cât și unul de intrare. I4
7

I5
Macrocell I/O3
Programmable
AND array
7
I6 Macrocell I/O4

I7 7
Macrocell I/O5
I8
7
Macrocell I/O6
I9
PLCC Package 7
I/O1
Macrocell O2
0
Circuitele Programmable Logic Array (PLA)

•Ambele arii (AND, OR) sunt

programabile
•Se poate realiza orice
combinație AND/OR
•Comutatoare programabile la
intersecția linii-coloane
•Ieșirile Qn regiștri de tip D cu,
reacție la intrări
Circuitele Programmable Logic Array (PLA)
Exemplu de programare
PLA
•Să se implementeze
următoarele funcții:

Circuit cu:
-5 intrări (A,B,C,D,E) și
- 4 ieșiri (X,Y,W,Z).
Desenați circuitul rezultant
folosind porți logice !
Circuitele Programmable AND Logic (PAL)
(Programmable Array Logic)

• Aria AND programabilă,

aria SAU fixă
• Număr mai mic de
combinații AND/OR posibile
• Sunt necesare mai puține
comutatoare
• Mai rapid ca PLA
• Ieșirile Qn registre de tip D
ce pot fi întoarse la intrare
 Circuitele CPLD
Circuitele CPLD (complex programmable logic device) au multe arii de
blocuri logice (logic array blocks - LABs) care de fapt sunt mai multe
CLP-uri simple pe un circuit integrat. Blocurile LAB sunt conectate prin
interconexiuni programabile (programmable interconnect array (PIA).

Logic array Logic array

I/O block (LAB) block (LAB) I/O
Logica este implementată în SPLD SPLD

CPLD și interconectată sunt

PIA
determinate printr-o descriere Logic array Logic array
într-un limbaj hardware – I/O block (LAB) block (LAB) I/O
SPLD SPLD
harware description language
(HDL).

Logic array Logic array

I/O block (LAB) block (LAB) I/O
SPLD SPLD
 Circuitele CPLD

General-purpose inputs

I/O Logic array block PIA Logic array block I/O

control (LAB A) (LAB B) control
I/O pins
block I/O pins
block
Macrocell 1 Macrocell 1

8Ð16 Macrocell 2 36 36 Macrocell 2 8-16

16 16

Macrocell 16 Macrocell 16
8-16 8-16
 Circuitele CPLD

Macrocelule din seria Altera MAX 7000 pot genera până la 5 termeni
de tip produs. Pentru expresii care necesită mai mulți termeni, ieșirile
pot fi expandate.

Parallel expanders
from other
macrocells

Product-term To I/O
selection Associated
logic control
matrix block
Expander example
A
B
C ABC(E + F)=ABCE + ABCF
Shared
expander

36 lines from PIA 15 expander

product terms E +F
from other EF Product term from another
macrocells macrocell in same LAB
 Macrocelulele

In plus față de logica combinațională, unele macrocelule au ieșirile disponibile

prin intermediul unor bistabile programabile. Aceasta permite circuitelor CPLD
să implementeze și logică secvențială

Global Global
Parallel expanders clear clock
from other
macrocells
From
MUX 5 I/O

To I/O
MUX 1 PRE
D/T Q
Product-
term C
selection
matrix MUX 2 EN
CLR

VCC MUX 3
Shared
expander

MUX 4
36 lines 15 expander product
from PIA terms from other
macrocells
 Circuitele FPGA

Un circuit FPGA (field programmable gate array) are o arhitectură diferită.

Elementul de bază este circuitul logic configurabil CLB (configurable logic block)
care este multiplicat în foarte multe exemplare.

CLB-urile sunt aranjate în linii

și coloane. În interiorul CLB CLB CLB

sunt module logice Logic module Logic module

interconectate. Modulele Logic module Logic module

logice sunt compuse din așa Logic module Logic module

numitele look-up table (LUT), Local Local
un flip-flop, și un MUX care interconnect interconnect

poate fi folosit pentru a Logic module Logic module

selecta semnalul de ieșire

direct sau prin intermediul flip-
flop-ului. Global column Global row
interconnect interconnect
 Circuitele FPGA

Logic modules can be configured for combinational logic, registered logic, or a

combination of both. The global interconnects distribute signals (including the
clock) to various CLBs.

FPGAs may also have a

CLB CLB
hard core portion of logic
Logic module Logic module
that is put in by the
Logic module Logic module
manufacturer and cannot
be reprogrammed by the Logic module Logic module

Local Local
user. These FPGAs are interconnect interconnect

useful in commonly used Logic module Logic module

functions such as I/O

interfaces.
Global column Global row
interconnect interconnect
Software-ul pentru programare logică

All manufacturers of programmable logic provide software to support their

products. The process is illustrated in the flowchart.

The first step is to enter

Design entry
the logic design into a Schematic
computer. It is done HDL
in one of two ways: Synthesis

1) Schematic entry Timing

Functional simulation
2) Hardware description simulation
language (HDL).
Implementation
Device
programming
(downloading)
Software-ul pentru programare logică
Design entry
Schematic
HDL

In schematic entry, the design is drawn on a computer screen by

placing components and connecting then with simulated wires. You do
not need to know the details of an HDL. After drawing the schematic, it
can be reduced to a single block symbol:
Software-ul pentru programare logică
Design entry
Schematic
HDL

In text entry, the design is entered via a hardware description language

such as VHDL or Verilog.

VHDL has two key parts: the entity A

and the architecture. The entity LED1
section describes the inputs, outputs,
and variables. The architecture B
section describes the relationships
between variables using Boolean
equations. The VHDL equation can be C
understood, even if you do not know D
VHDL.
For example, the VHDL expression for LED1 is written as
LED1 <= ((D XOR C) XOR B) XOR A;
Software-ul pentru programare logică
Design entry
Schematic
HDL

VHDL allows you to describe components in one program and then

use them in another program.

For example, an active-LOW S-R latch can be drawn as

S Q Q
A

Q QNot
B R

The complete VHDL program for this component is shown on

the following slide…..
 Software-ul pentru programare logică
Design entry
Schematic S Q Q
HDL A

entity S_RLatch is Q QNot

Entity port (A, B: in bit; Q, QNot: inout bit); R
B
section end entity S_RLatch;

Input and output variable

architecture Behavior of S_RLatch is names and types
begin
Q <= not A or not QNot;
Architecture QNot <= not B or not Q;
section end architecture Behavior;

} Boolean descriptions
of circuit

Assigns expression on
right to variable on left
 Simulare funcțională
Functional
simulation

After entering the circuit into an HDL (such as VHDL), the circuit is
tested in a functional simulation. The functional simulation is part of
the HDL. You can test the circuit with waveforms to verify the
operation.

The following shows the functional test of a counter

using a waveform editor:
 Sinteza
Synthesis

After the simulation, the computer program optimizes the logic by

eliminating redundant terms and generating a netlist, (a connection
list) that is a complete description of the circuit.

net1
net5
Netlist
net2 and1
net3 Netlist (Logic3)
net4 net<name>: instance<name>, <from>; <to>;
net6 instances: and1, and2, and3, and4, and5, or1, inv2,
net7 and2 net10 inv3, inv4;
Input/outputs: I1, I2, I3, I4, O1;
net9 net8 net1: and1, inport1; I1;
net11 net2: and1, inport2; I2;
inv1 O1
I1 net12 and3 net15 or1 Z net3: and1, inport3; I3;
net14 net26 net4: and1, inport4; I4;
A0
net13 net5: and1, outport1; or1, inport1;
inv2 net6: and2, inport1; I1;
I2 net16
net17 net20 net7: and2, inport2; I3;
A1 net18 and4 net8: and2, inport3; inv2,outport1
inv3 net19 net9: and2, inport4; inv4,outport1
I3 net23 net10: and2, outport1; or1,inport2;
A2 net11: and3, inport1; inv2,outport1
net21 net12: and3, inport2; inv3,outport1
inv4 net22 and5 net25
I4 net13: and3, inport3; I4;
A3 net14: and3, inport4; I1;
net24
5: and3
 Implementarea
Implementation

The computer next “maps” the design from the netlist to fit it to a
target device. Data for all potential target devices are in a software
library. The computer must account for the I/O pins and fit the logic to
the target device.
 Timing Simulation
Timing
simulation

After implementation, a timing simulation is done that takes into

account the specific delays in the target device and verifies that there
no problems with the timing. As in the case of the functional
simulation, the waveform editor can be used to review final timing.

Waveform Editor

Name: 1 ms 4 ms 8 ms 12 ms 16 ms
If a problem is revealed, it
A0 0
is not too late to correct it A1 0
before downloading the A2 0
file. A3 0
Glitch
Z X
 Programarea dispozitivului
Device
programming
(downloading)

The final step is to send the programming file from the computer to the
target device and test the implementation.

A PLDT-2 prototyping board

that has an Altera PLD as
the target device is shown.
Connections are added to
the board from a pulse
generator and oscilloscope
to test the actual circuit in a
laboratory environment.
The prototyping board has
built-in power supplies,
interfacing, I/O, and more.
 Testarea

The traffic light system application

was described in several System
Application Activities in the text.
The photograph is the traffic light
logic downloaded to a PLDT-2
board and operating a simulated
traffic light. An interface is added
to allow for the voltage and current
requirements of the bulbs.

PLDT-2 board Interface

board
 Boundary Scan Logic

Boundary scan that is designed by the manufacturer of programmable

devices to provide a means of testing and programming the device
without requiring physical access to the internal logic. Programmable
devices that are compliant with a certain standard have internal
registers to allow testing of internal interconnections and logic. Test data
is supplied and verified. When the circuit is operating, the boundary
scan logic is “invisible”.

The following slide shows a boundary scan logic diagram…

 Boundary Scan Logic
Instruction register MUX 2

TDO

Instruction Data/Instruction
decoder register select lines
OE

TAP control logic BS/ID/BP register select lines

UPDATEIR BS register parallel data I/O select

CLOCKIR
TMS SHIFTIR

TCK UPDATEDR
CLOCKDR
SHIFTDR
Boundary scan (BS) register

Identification (ID) register

MUX 1
TDI

Bypass (BP) register

Data registers (optional)

 Selected Key Terms

PAL A type of one-time programmable SPLD that consists of a

programmable array of AND gates that connects to a fixed array of OR
gates.

GAL A reprogrammable type of SPLD that that is similar to a PAL

except it uses a reprogrammable process technology, such as
EEPROM instead of fuses.
Macrocell
Part of a PAL, GAL, or CPLD that generally consists of one OR gate
and some associated output logic.
CPLD

A complex reprogrammable logic device that consists basically of

multiple SPLD arrays with programmable interconnections.
 Selected Key Terms

FPGA Field programmable gate array; a programmable logic device that

uses the LUT as the basic logic element and generally employs
either the antifuse or SRAM-based process technology

Design flow The process or sequence carried out to program a target device.

Schematic entry
A method of placing a logic design into software using schematic
Text entry symbols.

A method of placing a logic design into software using a hardware

Boundary description language (HDL).
scan
A method for internally testing a PLD based on the JTAG
standard (IEEE Std. 1149.1).
1. An advantage of PLDs over discrete circuits is
a. lower power and space requirements
b. higher reliability
c. design flexibility
d. all of the above
2. The logic expression for X is
a. X = B(A + B)
b. X = B + AB
c. X = B + AB
d. X = B(A + B)

A A B B

X
3. Generic Array Logic (GAL)
a. is reprogrammable
b. uses look-up tables for combinational logic
c. uses SRAM technology
d. all of the above
4. A general block of a CPLD is shown. The center (unmarked) block
represents a
a. configurable logic block (CLB)
b. programmable interconnect array (PIA)
c. comparator
d. look-up table (LUT)
Logic array Logic array
I/O block (LAB) block (LAB) I/O
SPLD SPLD

Logic array Logic array

I/O block (LAB) block (LAB) I/O
SPLD SPLD

Logic array Logic array

I/O block (LAB) block (LAB) I/O
SPLD SPLD
5. The diagram represents
a. a PIA
Parallel expanders
from other
b. an FPGA macrocells

c. a logic module
Product-term To I/O
d. a macrocell selection
matrix
Associated
logic control
block

Shared
expander

36 lines from PIA 15 expander

product terms