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3. Logic-Level Design for One Bit of the 1-Bus SRC ALU (pag.153):
Bandol Roxana-Nicoleta
6. Microprocesor pe 8 biti
Balan Gheorghe
Ovidiu Gurita
Alexandru Dascalu
Tan Bogdan
7. Pipelining
Milea Mihaela
Ignat Mihai
Cozmiuc Dana-Mihaela
Olenici Marius
19. Proiectare la nivel logic pe 1 bit pentru ALU SRC cu o magistrală (fig. 4.8)
Soiman Andrei
Popeanu Marina
Tcaciuc Beniamin
35. Logic Diagram and Symbol for a Master-Slave J-K Flip-Flop (fig. A.61)
Tudosi Andrei-Daniel
Galan Ionut-Florentin
Juravle Sergiu
42. First clock cycle: add enters stage 1 of the pipeline (Fig. 5.8)
Buzduga Lucian
Mihoc Ioana
Stavovei Ciprian
44. The Pipeline Data Path with Selected Control Signals (fig. 5.7)
Murarasu Liviu-Daniel
Miron Emanuel Danut
Torac Georgiana Paraschiva