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Electronica Digitala Laborator
Electronica Digitala Laborator
LABORATOR
Laborator
Prezentarea pupitrului pentru realizarea experimentelor NX 4i
1
3
4
5
14
6
7
8
9
13
11
15
12
Fig. 1
ELECTRONIC DIGITAL
LABORATOR
8. Circuit de control a unui echipament cu consum de curent important (ex. motor pas
cu pas ) ;
9. Sursa de tensiune reglabil de referin 0 5 V;
10. Convertor semnal analog digital;
11. Doua comutatoare(generatoare de semnal dreptunghiular) de semnal logic;
12. 8 comutatoare logice cu indicator ;
13. Generator de semnal n banda 1Hz-100kHz cu selectare a trei forme de und:
sinusoidala, dreptunghiulara si triunghiulara i reglaj al amplitudii i frecvenei.
14. Tensiunide alimentare de +/-12V si +/-5V la 1 A
15. Banc de lucru cu 1600 de puncte de conexiune pentru experimente
Pentru realizarea experimentelor se folosesc i urmtoarele aparate de msur a
parametrilor:
Multimetru digital DVM 300 cu caracteristicile : msoar tensiuni continue pn la
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ELECTRONIC DIGITAL
LABORATOR
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ELECTRONIC DIGITAL
LABORATOR
Laboratorul nr. 1
Prezentarea pupitrului de experimente, utilizarea osciloscopului i a multimetrului
Studenii vor studia pupitrul de experimente NX -4i cu prile lui componente pentru a
efectua experimente ulterioare. Cu ajutorul osciloscopului vor efectua vizualizri i
msurtori a semnalului generat de modulul 13 al pupitrului, pentru diferite valori ale
frecvenei, formei i amplitudini semnalului.
nainte de efectuarea msurtorilor, osciloscopul trebuie calibrat utiliznd ieirea 39 a
osciloscopului de semnal dreptunghiular de calibrare 0.2 Vpp i comutatorul 40 de selectare a
frecvenei.
Cu ajutorul multimetrului digital DVM 300 vor msura valoarea semnalului logic 1-0
generat de modulul de 8 comutatoare logice cu indicator (12) a pupitrului.
Se vor realiza urmtoarele scheme logice:
Fig
1
Fig
2
Pentru realizarea lor se va folosi circuitul HC7400N. Se va studia anexa ndrumarului
de laborator pentru a se identifica caracteristicile tehnice ale circuitului.
Circuitul HC7400N se va dispune pe bancul de lucru al pupitrului, se va alimenta cu
tensiune de + 5V i se va lega la mas, realizndu-se legtura electric ntre pinii circuitului i
sursa de tensiune a pupitrului cu ajutorul conductoarelor. Conectarea intrrilor la circuitele
logice se va realiza la ieirile comutatoarelor logice (12) ale pupitrului. Ieirea circuitului
logic se va conecta la unul din ledurile pupitrului (2).
Dup realizarea schemei, punerea n funciune a pupitrului se va face numai dup
verificarea ei de cadrul didactic. Cu ajutorul comutatoarelor logice de la intrrile circuitului
logic se vor realiza toate combinaiile logice posibile urmrindu-se funcionare lui prin
valoarea semnalului logic de la ieire evideniat cu ajutorul ledului.
n cadrul celei dea doua scheme se va msura cu multimetrul digital i osciloscopul
valoarea semnalului logic VOH i VOL (1 i 0 logic) .
Tot cu osciloscopul se va msura frecvena semnalului aplicat la intrarea circuitelor
logice precum i defazajul care apare ntre semnalul aplicat la intrare i cel de la ieire.
Referatul de laborator trebuie s conin noiunile noi nvate n cadrul acestei
lucrri de laborator i valorile parametrilor msurai cu cele doua aparate de msur,
multimetrul digital i osciloscopul.
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ELECTRONIC DIGITAL
LABORATOR
Laboratorul nr. 2
Determinarea caracteristicilor circuitelor logice bipolare
Aceast lucrare de laborator are ca obiect studiul parametrilor circuitelor TTL
standard i determinarea caracteristicilor porii logice fundamentale. Pentru aceasta se va
folosi pupitrul experimental NX -4i, o surs dubl de alimentare, multimetre digitale i
osciloscop cu 2 canale.
1. Se realizeaz montajul din figura urmtoare. La intrarea porii I-NU cu intrrile
conectate mpreun se aplic o tensiune continu, variabil ntre 0 i 5V, iar valorile msurate
ale tensiunii de ieire se trec ntr-un tabel. Se reprezint punct cu punct caracteristica static
de transfer Vout = f(Vin)
ELECTRONIC DIGITAL
LABORATOR
intrare I IL . Acest 1 logic este de 4,5V, valoare n general superioar lui VOH . Valorile obinute
trebuie s fie n concordan cu datele de catalog:
I IL I ILMAX = 1.6mA
I IH I IHMAX = 40 A
Laboratorul nr. 3
Determinarea caracteristicilor circuitelor logice MOS
5. Se msoar timpii de propagare prin poart cu ajutorul montajului din figura
urmtoare. Generatorul furnizeaz la intrare impulsuri TTL cu frecvena de circa 1MHz.
Circuitul de ieire (CL 15 pF ) simuleaz ncrcarea porii cu o sarcin echivalent cu 10
intrri TTL standard. Se msoar timpii de propagare i pentru CL 220 pF i se compar
rezultatele. Dac performanele osciloscopului nu sunt satisfctoare pentru efectuarea
msurtorii, se poate ncerca nserierea mai multor pori identice i medierea rezultatelor
astfel obinute.
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ELECTRONIC DIGITAL
LABORATOR
Laboratorul nr. 3
Determinarea caracteristicilor circuitelor logice MOS
Aceast lucrare de laborator are ca obiect studiul parametrilor circuitelor CMOS i
determinarea caracteristicilor porii logice fundamentale. Pentru aceasta se va folosi pupitrul
experimental NX -4i, o surs dubl de alimentare, multimetre digitale i osciloscop cu 2
canale.
1. Se realizeaz montajul din figura urmtoare. La intrarea porii I-NU cu intrrile
conectate mpreun se aplic o tensiune continu, variabil ntre 0 i 5V, iar valorile msurate
ale tensiunii de ieire se trec ntr-un tabel. Se reprezint punct cu punct caracteristica static
de transfer Vout = f(Vin). Se repet msurtorile pentru V CC 10 i pentru V CC 15 , iar cele
trei caracteristici se reprezint pe acelai grafic. Se msoar nivelele logice i se compar cu
valorile garantate prin standard.
ELECTRONIC DIGITAL
LABORATOR
ELECTRONIC DIGITAL
LABORATOR
Laboratorul nr. 4
Studierea circuitului poart
n cadrul acestei lucrri de laborator se va studia funcionarea circuitului poart
prezentat n cadrul orelor de curs . Cu ajutorul pupitrului de experimente NX 4i i utiliznd
circuite integrate care ncorporeaz pori logice AND i NAND de exemplu SN74HC08 sau
SN74HC00 se vor realiza schemele circuitelor. Se va studia anexa ndrumarului de laborator
pentru a se identifica caracteristicile tehnice ale circuitelor folosite.
Pentru circuitul de tip poart se vor folosi dou scheme prezentate mai jos:
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ELECTRONIC DIGITAL
LABORATOR
Laboratorul nr. 5
Studierea circuitului de selecie
n cadrul acestei lucrri de laborator se va studia funcionarea circuitului de selecie
prezentat n cadrul orelor de curs . Cu ajutorul pupitrului de experimente NX 4i i utiliznd
circuite integrate care ncorporeaz pori logice AND i NOT de exemplu SN74HC08,
SN74HC20, SN74HC04 se vor realiza schemele circuitelor. Se va studia anexa ndrumarului
de laborator pentru a se identifica caracteristicile tehnice ale circuitelor folosite.
Circuitul de selecie ce va fi studiat n cadrul acestui laborator va fi cel ce va selecta
valoarea 89(10) (1011001(2)) din cele 128 valori posibile ce pot fi aplicate la intrare. Funcia
logic a circuitului va fi:
Y = X 6 X 5 X 4 X 3 X 2 X1 X 0
Schema circuitului este urmtoarea:
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ELECTRONIC DIGITAL
LABORATOR
Laboratorul nr. 6
Studierea funcionrii circuitului de decodificare
n cadrul acestei lucrri de laborator se va realiza i se va studia funcionarea
circuitului decodificator 1 din 4 prezentat n cadrul orelor de curs. Cu ajutorul pupitrului de
experimente NX 4i i utiliznd circuitele integrate care ncorporeaz pori logice AND cu 2
intrri i NOT de ex: SN74HC08 i SN74HC04 se va realiza schema circuitului prezentat
mai jos. Se va studia anexa ndrumarului de laborator pentru a se identifica caracteristicile
tehnice ale circuitelor folosite.
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ELECTRONIC DIGITAL
LABORATOR
Laboratorul nr. 7
Utilizarea programului Digital Works n studiul circuitelor digitale.
Programul Digital Works este un program gratuit, foarte uor de folosit n studiul i
simularea funcionrii circuitelor digitale studiate n cadrul orelor de curs. Interfaa
programului este prezentat mai jos:
Bar de circuite
Spaiu de execuie
a circuitului
Realizarea unei scheme utiliznd acest soft este foarte simpl. Se d click cu mousul
pe simbolul circuitului logic necesar si apoi se d din nou click pe spaiul de lucru unde dorim
s plasm circuitul. Circuitul respectiv poate fi ters, dac dorim prin selectarea lui cu un
click de mouse i apoi apsarea tastei del. De asemenea el poate fi mutat pe spaiul de lucru i
rotit cu ajutorul mousului.
Dup plasarea componentelor se realizeaz conexiunea prin trasarea firelor de
legtur. Acest lucru se efectueaz cu ajutorul creionului din bara de butoane. La
apropierea de un punct de legtur valid softul afieaz un stegule wire anunnd
posibilitatea de a da click cu butonul stng al mousului pentru a ncepe desenarea firului.
Terminarea conexiunii se realizeaz, fr a se ine apsat butonul mousului, prin efectuarea
unui nou click atunci cnd apare steguleul respectiv la apropierea de punctul de conexiune
dorit.
Dup terminarea de desenat a schemei se simuleaz funcionarea circuitului electronic
digital cu ajutorul butoanelor din bara de rulare. Cu ajutorul butonului 1 se pot comanda
generatoarele de semnal logic.
Pentru a experimenta utilizarea acestui soft studenii trebuie s realizeze i s
simuleze schemele circuitelor logice de la laboratorul 1.
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ELECTRONIC DIGITAL
LABORATOR
Laboratorul nr. 8
Simularea funcionrii circuitelor poart i de selecie
cu ajutorul programului Digital Works
n cadrul acestui laborator se va studia funcionarea circuitelor poart i de selecie
prezentate n cadrul orelor de curs i studiate n cadrul unui laborator precedent.
Cu ajutorul programului Digital Works se va desena schema fiecrui circuit n parte i
se va simula funcionarea lui urmnd s se ntocmeasc tabela de adevr a circuitelor.
Pentru circuitul de tip poart se vor folosi dou scheme prezentate mai jos:
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ELECTRONIC DIGITAL
LABORATOR
Laboratorul nr. 9
Simularea funcionrii circuitelor multiplexor i demultiplexor
cu ajutorul programului Digital Works
n cadrul acestui laborator se va studia funcionarea circuitelor multiplexor i
demultiplexor prezentate n cadrul orelor de curs.
Cu ajutorul programului Digital Works se va desena schema fiecrui circuit n parte i
se va simula funcionarea lui urmnd s se ntocmeasc tabela de adevr a circuitelor.
1. Circuitul Multiplexor 22 : 1
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ELECTRONIC DIGITAL
LABORATOR
Laboratorul nr. 10
Studiul funcionrii circuitului multiplexor
n cadrul acestei lucrri de laborator se va realiza i se va studia funcionarea
circuitului multiplexor studiat n cadrul laboratorului precedent. n
prima
parte
a
laboratorului studenii se va realiza schema circuitului multiplexor simulat la ora de laborator
precedent.
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ELECTRONIC DIGITAL
LABORATOR
Laboratorul nr. 11
Studiul circuitelor basculante bistabile
n cadrul acestei lucrri de laborator se vor studia funcionarea circuitelor basculante
bistabile de tip JK, D, T, pentru fiecare circuit n parte se vor ntocmi tabele de adevr . Cu
ajutorul pupitrului de experimente NX 4i i utiliznd circuite integrate care ncorporeaz
bistabile de tip JK, de exemplu CD74HC73 sau SN74LS73 se vor realiza schemele
circuitelor. Se va studia anexa ndrumarului de laborator pentru a se identifica caracteristicile
tehnice ale circuitelor folosite.
Circuitul basculant bistabil sincron JK:
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ELECTRONIC DIGITAL
LABORATOR
Laboratorul nr. 12
Studiul circuitelor logice secveniale de tip numrtor
Cu ajutorul softului Digital Works se va simula i studia funcionarea circuitelor
secveniale de tip numrtor sincron sau asincron care genereaz la ieire o secven de
numere binare.
Pentru studierea funcionrii unui numrtor asincron de trei bii se va folosi schema
urmtoare:
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ELECTRONIC DIGITAL
LABORATOR
Laboratorul nr. 13
Realizarea unui numrtor programabil
n cadrul acestui laborator se va realiza i studia funcionarea unui circuit logic
secvenial de tip numrtor asincron, pe trei bii, programabil. Programarea numrtorului,
implic posibilitatea ca numrtorul s nceap s numere de la o valoare 0<n<7 aleas i
impus numrtorului prin pinii de comand PRESET ai circuitului basculant bistabil de tip
JK.
Schema circuitului numrtor programabil este prezentat n figura de mai jos:
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ELECTRONIC DIGITAL
LABORATOR
Laboratorul nr. 14
Studiul registrului de deplasare
n cadrul acestui laborator se va realiza i studia funcionarea unui circuit logic
secvenial de tip registru serial de patru bii cu deplasare la dreapta cu cele dou moduri de
funcionare, ncrcare paralel a datelor n registru i deplasarea lor la dreapta. Acest circuit
logic secvenial fiind studiat la orele de curs.
Pentru realizarea lui se va folosi schema prezentat n figura urmtoare:
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ELECTRONIC DIGITAL
LABORATOR
Laboratorul nr. 15
Tabelul de adevr ale circuitelor logice bipolare
AND, NAND, OR, NOR, XOR, XNOR
n cadrul acestei lucrri de laborator se vor realiza circuitele cu ajutorul crora se vor
studia tabelele de adevr ale circuitelor logice AND, NAND, OR, NOR, XOR, XNOR.
Pentru realizare lor se vor utiliza circuitele integrate 74HC08, 74HC00, 74HC32, 74HC02,
74HC04 i 74HC86.
Se va studia anexa ndrumarului de laborator pentru a se identifica caracteristicile
tehnice ale circuitelor folosite.
Pentru realizarea montajelor se vor folosi urmtoarele scheme:
a) circuitul AND, NAND
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ELECTRONIC DIGITAL
LABORATOR
Laboratorul nr. 16
Simularea funcionrii circuitelor celul sumator 1 bit
cu ajutorul programului Digital Works
n cadrul acestui laborator se va studia funcionarea circuitului celul sumator ce
efectueaz operaia de adunare dintre doi operanzi pe 1 bit, prezentat n cadrul orelor de curs.
Cu ajutorul programului Digital Works se va desena schema circuit i se va simula
funcionarea lui urmnd s se ntocmeasc tabela de adevr.
Celula sumator pe un bit efectueaz operaia de adunare ntre doi operanzi pe un bit
(A0 + B0) acceptnd i posibilitatea apariiei unui transport de la un calcul precedent (T0).
Rezultatul adunrii va fi afiat la ieirile C0 i T1(C1). Schema circuitului este prezentat mai
jos. Se vor aplica semnale logice la cele trei intrri urmrindu-se corectitudinea operaiei de
adunare prin valorile obinute la ieire.
Utilitatea acestei scheme este dat de posibilitatea efecturii operaiei de adunare ntre
doi operanzi exprimai pe un numr oarecare de bii utiliznd un numr de celule egal cu
numrul de bii al operanzilor, conectate ntre ele prin ieirea T1 a primei celule i intrarea T0
a celulei urmtoare.
C0
T0
C1
T0
T1
B0
A0
T1
B1
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A1
ELECTRONIC DIGITAL
LABORATOR
Laboratorul nr. 17
Studiul funcionrii circuitului demultiplexor
n cadrul acestei lucrri de laborator se va realiza i se va studia funcionarea
circuitului demultiplexor studiat n cadrul laboratorului precedent. n
prima
parte
a
laboratorului studenii se va realiza schema circuitului demultiplexor simulat la o or de
laborator precedent. Cu ajutorul pupitrului de experimente NX 4i i utiliznd circuitele
integrate care ncorporeaz pori logice AND, NOT i OR de ex: SN74HC08, SN74HC20,
SN74HC32 i SN74HC04 se va realiza schema circuitului. Se va studia anexa ndrumarului
de laborator pentru a se identifica caracteristicile tehnice ale circuitelor folosite.
Schema circuitului multiplexor este urmtoarea:
ELECTRONIC DIGITAL
LABORATOR
ELECTRONIC DIGITAL
LABORATOR
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ANEXA 1
ANEXA 2
ANEXA 3
ANEXA 4
MC54/74F151
8-INPUT MULTIPLEXER
The MC54/74F151 is a high-speed 8-input digital multiplexer. It provides in
one package, the ability to select one line of data from up to eight sources. The
F151 can be used as a universal function generator to generate any logic
function of four variables. Both asserted and negated outputs are provided.
The F151 is a logic implementation of a single pole, 8-position switch with
the switch position controlled by the state of three Select inputs, S0, S1, S2.
The Enable input (E) is active LOW. The logic function provided at the output
is:
8-INPUT
MULTIPLEXER
FAST SHOTTKY TTL
Z = E (I0 S0 S1 S2 + I1 S0 S1 S2 +
I2 S0 S1 S2 + I3 S0 S1 S2 +
I4 S0 S1 S2 + I5 S0 S1 S2 +
I6 S0 S1 S2 + I7 S0 S1 S2)
J SUFFIX
CERAMIC
CASE 620-09
I4
I5
I6
I7
S0
S1
16
15
14
13
12
11
10
16
S2
9
N SUFFIX
PLASTIC
CASE 648-08
16
1
I3
I2
I1
I0
GND
LOGIC DIAGRAM
I0
I1
I2
I3
D SUFFIX
SOIC
CASE 751B-03
16
I4
I5
I6
I7
S2
S1
ORDERING INFORMATION
MC54FXXXJ
MC74FXXXN
MC74FXXXD
S0
E
Ceramic
Plastic
SOIC
LOGIC SYMBOL
Z Z
12
13
14
15
1
2
3
4
7
FUNCTION TABLE
Inputs
E
H
L
L
L
L
L
L
L
L
S2
X
L
L
L
L
H
H
H
H
Outputs
S1
X
L
L
H
H
L
L
H
H
S0
X
L
H
L
H
L
H
L
H
Z
H
I0
I1
I2
I3
I4
I5
I6
I7
Z
L
I0
I1
I2
I3
I4
I5
I6
I7
I7
I6
I5
Z
I4
I3
I2
I1
Z
I0
ES S S
0 1 2
11 10 9
VCC = PIN 16
GND = PIN 8
May 1989
Features
Each of these 4-line-to-16-line decoders utilizes TTL circuitry to decode four binary-coded inputs into one of sixteen
mutually exclusive outputs when both the strobe inputs G1
and G2 are low The demultiplexing function is performed
by using the 4 input lines to address the output line passing
data from one of the strobe inputs with the other strobe
input low When either strobe input is high all outputs are
high These demultiplexers are ideally suited for implementing high-performance memory decoders All inputs are buffered and input clamping diodes are provided to minimize
transmission-line effects and thereby simplify system design
Y
Y
Y
TL F 63941
TL F 6394 2
TL F 6394
RRD-B30M105 Printed in U S A
ANEXA 5
ANEXA 6
D
D
D
D
147, LS147
Encodes 10-Line Decimal to 4-Line BCD
Applications Include:
Keyboard Encoding
Range Selection
148, LS148
Encodes 8 Data Lines to 3-Line Binary
(Octal)
Applications Include:
N-Bit Encoding
Code Converters and Generators
ANEXA 7
ANEXA 8
DM74LS83A
4-Bit Binary Adder with Fast Carry
General Description
Features
Ordering Code:
Order Number
DM74LS83AN
Package Number
N16E
Package Description
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Connection Diagram
DS006378
www.fairchildsemi.com
August 1986
ANEXA 9
DM74LS83A
Truth Table
Logic Diagram
www.fairchildsemi.com
ANEXA 10
ANEXA 11
SN54LS169B, SN54S169
SN74LS169B, SN74S169
SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTERS
SDLS134 OCTOBER 1976 REVISED MARCH 1988
SN54LS169B, SN54S169
SN74LS169B, SN74S169
SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTERS
SDLS134 OCTOBER 1976 REVISED MARCH 1988
SN54LS169B, SN54S169
SN74LS169B, SN74S169
SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTERS
SDLS134 OCTOBER 1976 REVISED MARCH 1988
SN54LS169B, SN54S169
SN74LS169B, SN74S169
SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTERS
SDLS134 OCTOBER 1976 REVISED MARCH 1988
SN54LS169B, SN54S169
SN74LS169B, SN74S169
SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTERS
SDLS134 OCTOBER 1976 REVISED MARCH 1988
ANEXA 12
SN54HC00, SN74HC00
QUADRUPLE 2-INPUT POSITIVE-NAND GATES
ANEXA 13
D
D
D
SN54HC00 . . . J OR W PACKAGE
SN74HC00 . . . D, DB, N, NS, OR PW PACKAGE
(TOP VIEW)
1
14
13
12
11
10
Typical tpd = 8 ns
4-mA Output Drive at 5 V
Low Input Current of 1 A Max
1B
1A
NC
VCC
4B
SN54HC00 . . . FK PACKAGE
(TOP VIEW)
VCC
4B
4A
4Y
3B
3A
3Y
1Y
NC
2A
NC
2B
3 2 1 20 19
18
17
16
15
14
9 10 11 12 13
4A
NC
4Y
NC
3B
2Y
GND
NC
3Y
3A
1A
1B
1Y
2A
2B
2Y
GND
D
D
D
NC No internal connection
description/ordering information
The HC00 devices contain four independent 2-input NAND gates. They perform the Boolean function
Y = A B or Y = A + B in positive logic.
ORDERING INFORMATION
PACKAGE
TA
PDIP N
ORDERABLE
PART NUMBER
Tube of 25
Tube of 50
SN74HC00D
Reel of 2500
SOIC D
SN74HC00N
SN74HC00DR
TOP-SIDE
MARKING
SN74HC00N
HC00
Reel of 250
SN74HC00DT
SOP NS
Reel of 2000
SN74HC00NSR
HC00
SSOP DB
Reel of 2000
SN74HC00DBR
HC00
Tube of 90
SN74HC00PW
Reel of 2000
SN74HC00PWR
Reel of 250
SN74HC00PWT
CDIP J
Tube of 25
SNJ54HC00J
SNJ54HC00J
CFP W
Tube of 150
SNJ54HC00W
SNJ54HC00W
LCCC FK
40C 85C
40 C to 85 C
Tube of 55
SNJ54HC00FK
TSSOP PW
55C 125C
55 C to 125 C
HC00
SNJ54HC00FK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2003, Texas Instruments Incorporated
SN54HC00, SN74HC00
QUADRUPLE 2-INPUT POSITIVE-NAND GATES
SCLS181E DECEMBER 1982 REVISED AUGUST 2003
FUNCTION TABLE
(each gate)
INPUTS
OUTPUT
Y
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Package thermal impedance, JA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86C/W
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65C to 150C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
SN74HC00
MIN
VCC
VIH
VCC = 2 V
VCC = 4.5 V
VCC = 6 V
VCC = 2 V
VIL
VI
VO
NOM
MAX
3.15
3.15
UNIT
V
1.5
V
4.2
0.5
0.5
1.35
VCC = 4.5 V
VCC = 6 V
1.35
1.8
0
Output voltage
Input transition rise/fall time
MIN
1.5
4.2
Input voltage
t/v
t/ v
MAX
Supply voltage
NOM
0
VCC = 2 V
VCC = 4.5 V
VCC
VCC
1.8
0
0
VCC
VCC
1000
500
1000
500
ns
VCC = 6 V
400
400
TA
Operating free-air temperature
55
125
40
85
C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
SN54HC04, SN74HC04
HEX INVERTERS
ANEXA 14
D
D
D
D
D
D
Typical tpd = 8 ns
4-mA Output Drive at 5 V
Low Input Current of 1 A Max
SN54HC04 . . . J OR W PACKAGE
SN74HC04 . . . D, N, NS, OR PW PACKAGE
(TOP VIEW)
1
14
13
12
11
10
1Y
1A
NC
VCC
6A
VCC
6A
6Y
5A
5Y
4A
4Y
2A
NC
2Y
NC
3A
3 2 1 20 19
18
17
16
15
14
9 10 11 12 13
6Y
NC
5A
NC
5Y
3Y
GND
NC
4Y
4A
1A
1Y
2A
2Y
3A
3Y
GND
SN54HC04 . . . FK PACKAGE
(TOP VIEW)
NC No internal connection
description/ordering information
The HC04 devices
Y = A in positive logic.
contain
six
independent
inverters.
They
perform
the
Boolean
function
ORDERING INFORMATION
ORDERABLE
PART NUMBER
PACKAGE
TA
PDIP N
TOP-SIDE
MARKING
Tube of25
SN74HC04N
Tube of 50
SN74HC04D
Reel of 2500
SN74HC04DR
Reel of 250
SN74HC04DT
Reel of 2000
SN74HC04NSR
Tube of 90
SN74HC04PW
Reel of 2000
SN74HC04PWR
Reel of 250
SN74HC04PWT
CDIP J
Tube of 25
SNJ54HC04J
SNJ54HC04J
CFP W
Tube of 150
SNJ54HC04W
SNJ54HC04W
LCCC FK
Tube of 55
SNJ54HC04FK
SOIC D
40C to 85C
40C
SOP NS
TSSOP PW
55C to 125C
SN74HC04N
HC04
HC04
HC04
SNJ54HC04FK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
FUNCTION TABLE
(each inverter)
INPUT
A
OUTPUT
Y
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2003, Texas Instruments Incorporated
SN54HC04, SN74HC04
HEX INVERTERS
SCLS078D DECEMBER 1982 REVISED JULY 2003
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Package thermal impedance, JA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65C to 150C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
SN74HC04
MIN
VCC
VIH
VCC = 2 V
VCC = 4.5 V
MIN
NOM
MAX
1.5
3.15
UNIT
V
1.5
3.15
4.2
VCC = 6 V
VCC = 2 V
VIL
MAX
Supply voltage
NOM
4.2
0.5
Input voltage
Output voltage
t/v
VCC = 2 V
VCC = 4.5 V
1.35
1.8
VI
VO
0.5
1.35
VCC = 4.5 V
VCC = 6 V
1.8
VCC
VCC
0
0
VCC
VCC
500
V
V
1000
500
400
VCC = 6 V
1000
400
ns
TA
Operating free-air temperature
55
125
40
85
C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
SN54HC20, SN74HC20
DUAL 4INPUT POSITIVENAND GATES
ANEXA 15
SN54HC20 . . . FK PACKAGE
(TOP VIEW)
14
13
12
11
10
VCC
2D
2C
NC
2B
2A
2Y
NC
NC
1C
NC
1D
3 2 1 20 19
18
17
16
15
14
9 10 11 12 13
2C
NC
NC
NC
2B
1Y
GND
NC
2Y
2A
1B
1A
NC
VCC
2D
SN54HC20 . . . J OR W PACKAGE
SN74HC20 . . . D, DB, N, NS, OR PW PACKAGE
(TOP VIEW)
1A
1B
NC
1C
1D
1Y
GND
D Typical tpd = 11 ns
D 4-mA Output Drive at 5 V
D Low Input Current of 1 A Max
NC No internal connection
description/ordering information
The HC20 devices contain two independent 4-input NAND gates. They perform the Boolean function
Y = A B C D or Y = A + B + C + D in positive logic.
ORDERING INFORMATION
PACKAGE
TA
PDIP N
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
Tube of 25
SN74HC20N
Tube of 50
SN74HC20D
Reel of 2500
SN74HC20DR
Reel of 250
SN74HC20DT
SOP NS
Reel of 2000
SN74HC20NSR
HC20
SSOP DB
Reel of 2000
SN74HC20DBR
HC20
Tube of 90
SN74HC20PW
Reel of 2000
SN74HC20PWR
SOIC D
40 C 85C
40C to 85 C
TSSOP PW
SN74HC20N
HC20
HC20
Reel of 250
55 C 125C
55C to 125 C
SN74HC20PWT
CDIP J
Tube of 25
SNJ54HC20J
SNJ54HC20J
CFP W
Tube of 150
SNJ54HC20W
SNJ54HC20W
LCCC FK
Tube of 55
SNJ54HC20FK
SNJ54HC20FK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2003, Texas Instruments Incorporated
SN54HC20, SN74HC20
DUAL 4INPUT POSITIVENAND GATES
SCLS086F DECEMBER 1982 REVISED AUGUST 2003
FUNCTION TABLE
(each gate)
INPUTS
A
OUTPUT
Y
1
2
4
5
2A
2B
2C
2D
1Y
9
10
12
13
2Y
Pin numbers shown are for the D, DB, J, N, NS, PW, and W packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Package thermal impedance, JA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86C/W
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65C to 150C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
SN54HC32, SN74HC32
QUADRUPLE 2-INPUT POSITIVE-OR GATES
ANEXA 16
D
D
D
14
13
12
11
10
1B
1A
NC
VCC
4B
VCC
4B
4A
4Y
3B
3A
3Y
1Y
NC
2A
NC
2B
3 2 1 20 19
18
17
16
15
14
9 10 11 12 13
4A
NC
4Y
NC
3B
2Y
GND
NC
3Y
3A
Typical tpd = 8 ns
4-mA Output Drive at 5 V
Low Input Current of 1 A Max
SN54HC32 . . . FK PACKAGE
(TOP VIEW)
SN54HC32 . . . J OR W PACKAGE
SN74HC32 . . . D, DB, N, NS, OR PW PACKAGE
(TOP VIEW)
1A
1B
1Y
2A
2B
2Y
GND
D
D
D
NC No internal connection
description/ordering information
The HC32 devices contain four independent 2-input OR gates. They perform the Boolean function
A B in positive logic.
Y
A B or Y
+ )
ORDERING INFORMATION
PACKAGE
TA
PDIP N
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
Tube of 25
SN74HC32N
Tube of 50
SN74HC32D
Reel of 2500
SN74HC32DR
Reel of 250
SN74HC32DT
SOP NS
Reel of 2000
SN74HC32NSR
HC32
SSOP DB
Reel of 2000
SN74HC32DBR
HC32
Tube of 90
SN74HC32PW
Reel of 2000
SN74HC32PWR
Reel of 250
SN74HC32PWT
CDIP J
Tube of 25
SNJ54HC32J
SNJ54HC32J
CFP W
Tube of 150
SNJ54HC32W
SNJ54HC32W
LCCC FK
Tube of 55
SNJ54HC32FK
SOIC D
40C 85C
40 C to 85 C
TSSOP PW
55C 125C
55 C to 125 C
SN74HC32N
HC32
HC32
SNJ54HC32FK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2003, Texas Instruments Incorporated
SN54HC32, SN74HC32
QUADRUPLE 2-INPUT POSITIVE-OR GATES
SCLS200D DECEMBER 1982 REVISED AUGUST 2003
FUNCTION TABLE
(each gate)
INPUTS
B
OUTPUT
Y
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Package thermal impedance, JA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86C/W
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65C to 150C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
SN74HC32
MIN
VCC
VIH
VCC = 2 V
VCC = 4.5 V
VCC = 6 V
VCC = 2 V
VIL
VI
VO
NOM
MAX
3.15
3.15
UNIT
V
1.5
V
4.2
0.5
0.5
1.35
VCC = 4.5 V
VCC = 6 V
1.35
1.8
0
Output voltage
Input transition rise/fall time
MIN
1.5
4.2
Input voltage
t/v
t/ v
MAX
Supply voltage
NOM
0
VCC = 2 V
VCC = 4.5 V
VCC
VCC
1.8
0
0
VCC
VCC
1000
500
1000
500
ns
VCC = 6 V
400
400
TA
Operating free-air temperature
55
125
40
85
C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
SN54HC32, SN74HC32
QUADRUPLE 2-INPUT POSITIVE-OR GATES
SCLS200D DECEMBER 1982 REVISED AUGUST 2003
TEST CONDITIONS
VCC
MIN
TA = 25C
TYP
MAX
SN54HC32
SN74HC32
MIN
MIN
MAX
2V
VOH
VI = VIH or VIL
IOH = 4 mA
IOH = 5.2 mA
1.9
1.998
1.9
4.4
4.499
4.4
4.4
5.9
5.999
5.9
5.9
4.5 V
3.98
4.3
3.7
3.84
6V
5.48
5.8
5.2
UNIT
1.9
4.5 V
6V
IOH = 20 A
A
MAX
5.34
2V
IOL = 4 mA
IOL = 5.2 mA
II
ICC
VI = VCC or 0
VI = VCC or 0,
IO = 0
0.1
0.1
4.5 V
0.001
0.1
0.1
0.1
0.001
0.1
0.1
0.1
4.5 V
0.17
0.26
0.4
0.33
6V
0.15
0.26
0.4
0.33
6V
VI = VIH or VIL
0.1
6V
IOL = 20 A
A
VOL
0.002
0.1
100
1000
1000
nA
40
20
10
10
10
pF
6V
Ci
2 V to 6 V
SN54HC32
SN74HC32
MIN
MIN
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC
2V
50
100
150
125
tpd
A or B
4.5 V
10
20
30
25
6V
17
25
21
MIN
MAX
MAX
2V
Y
38
75
110
15
22
19
13
19
ns
95
4.5 V
6V
tt
UNIT
16
ns
TEST CONDITIONS
No load
TYP
20
UNIT
pF
SN54HC86, SN74HC86
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
ANEXA 17
D
D
D
D
D
D
D
SN54HC86 . . . J OR W PACKAGE
SN74HC86 . . . D, N, NS, OR PW PACKAGE
(TOP VIEW)
1
14
13
12
11
10
1B
1A
NC
VCC
4B
VCC
4B
4A
4Y
3B
3A
3Y
1Y
NC
2A
NC
2B
3 2 1 20 19
18
17
16
15
14
9 10 11 12 13
4A
NC
4Y
NC
3B
2Y
GND
NC
3Y
3A
1A
1B
1Y
2A
2B
2Y
GND
SN54HC86 . . . FK PACKAGE
(TOP VIEW)
NC No internal connection
description/ordering information
These devices contain four independent 2-input exclusive-OR gates. They perform the Boolean function
Y=A
B or Y = AB + AB in positive logic.
A common application is as a true / complement element. If one of the inputs is low, the other input is reproduced
in true form at the output. If one of the inputs is high, the signal on the other input is reproduced inverted at the
output.
ORDERING INFORMATION
PACKAGE
TA
PDIP N
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
Tube of 25
SN74HC86N
Tube of 50
SN74HC86D
Reel of 2500
SN74HC86DR
Reel of 250
SN74HC86DT
Reel of 2000
SN74HC86NSR
Tube of 90
SN74HC86PW
Reel of 2000
SN74HC86PWR
Reel of 250
SN74HC86PWT
CDIP J
Tube of 25
SNJ54HC86J
SNJ54HC86J
CFP W
Tube of 150
SNJ54HC86W
SNJ54HC86W
LCCC FK
Tube of 55
SNJ54HC86FK
SOIC D
40C 85C
40 C to 85 C
SOP NS
TSSOP PW
55C 125C
55 C to 125 C
SN74HC86N
HC86
HC86
HC86
SNJ54HC86FK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2003, Texas Instruments Incorporated
SN54HC86, SN74HC86
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
SCLS100E DECEMBER 1982 REVISED AUGUST 2003
FUNCTION TABLE
(each gate)
INPUTS
A
OUTPUT
Y
exclusive-OR logic
An exclusive-OR gate has many applications, some of which can be represented better by alternative logic
symbols.
Exclusive OR
=1
These are five equivalent exclusive-OR symbols valid for an HC86 gate in positive logic; negation may be
shown at any two ports.
Logic Identity Element
Even-Parity Element
2k
Odd-Parity Element
2k + 1
The output is active (high) if
an odd number of inputs (i.e.,
only 1 of the 2) are active.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Package thermal impedance, JA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65C to 150C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
BIBLIOGRAFIE