DE SEMNAL
CURS 4
Arhitectura procesoarelor
BlackFin.
Instruciuni ASM
Toma tefan-Adrian (cpt. dr. ing.)
Lector universitar (CS III)
Academia Tehnic Miltiar
Cuprins
Familia BlackFin
Familia BlackFin
Motor dual de
multiplicare i
acumulare (MAC)
Set de instruciuni RISC
(reduce-instructionset computer)
Capacitate de prelucrare
a semnalelor
multimedia
Adunare/scdere pe 16 bii
31
16
0
L
31
H
16
R1
0
R2
+
31
16
H
0
R3
31
16
31
16
R1
R2
+ -
- +
R3
R3 = R1 +|-R2, R4 = R1-|+R2;
R4
(operaie AND)
(operaie OR)
(operaie NOT)
(operaie XOR)
R1
R2
+
31
R3
R3 = R1+R2;
31
R1
R1
R2
R2
R4
R3 = R1+R2, R4 = R1-R2;
R3
L
31
R1
16
R2
31
R3
R3 = R1.L*R2.H;
R1
R2
+
31
A0.H
A0.L
A0 += R1.L*R2.L;
R1
R2
A0
A1
R3
31
16
R3.H=(A1-=R1.H*R2.H),R3.L=(A0+=R1.L*R2.L);
R0= [I0++M0];
R1= [I0++M0];
R2= [I0++M0];
R3= [I0++M0];
R3= [I0++M0];
// Acces 1
// Acces 2
// Acces 3
// Acces 4
// Acces 5